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Udi.Barzilai
I honestly don't see the point in measuring the distribution of _die_area_ ...
Myths, hype and the building blocks of SoCs
Brian Bailey
11/8/2012 6:21 PM EST
Further thoughts and conclusions
I’m wondering if he [that would be me] is confusing die area with the number of IP blocks being used. In the chart you used, it looks at the percent of die area dedicated for each category.
If you think about it, memory is pretty area efficient, so the impact of adding a lot of memory is less than if you added a lot of analog functions since the analog functions don’t scale all that well. However, if you were adding a great deal of memory, then I think the die area dedicated to memory would impact the percent of die area utilized for the memory.
Does this impact the die area dedicated to the increasing number of IP blocks being used? I think it depends on the types of IP blocks we are talking about. You can put a lot of different IP blocks on an SoC. However, if we are talking about a 5-6 billion-transistor SoC, the IP blocks won’t take up all that much die area. An ARM CPU core at 400K gates comes to mind. You can put a lot of them on such a chip without having much impact on total die area. This is some of my thinking behind having such a chart. If I remember correctly, when the ITRS originally came out with this chart, they had memory equal to 94% of die area, re-used logic at 4% and new logic at 2%. Their thinking was that on 10 billion transistor chips, no one would have any time to put a lot of new logic on it. 2% of 10B is 200M. Back then no one was building even 100M transistor chips, so I think they felt that the overwhelming majority of such an SoC was going to be either memory or re-used logic. It is a lot easier to emplace memory and replicate it over and over than to spend time designing new logic gates.
I always felt this was a very short-sighted view of how designers were going to design their parts. Essentially it said that logic designers were going to become memory designers and this was never going to happen.
Looking forward
So, the real question becomes: is true innovation in hardware being constrained by how much logic can be designed or have we already reached the plateau of what can be reasonably added in a new design without raising risk to unacceptable levels? How big an impact will ESL have on that? Will it allow an increase in novelty without adding risk? Is the system architecture and verification becoming the bottleneck?
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
I’m wondering if he [that would be me] is confusing die area with the number of IP blocks being used. In the chart you used, it looks at the percent of die area dedicated for each category.
If you think about it, memory is pretty area efficient, so the impact of adding a lot of memory is less than if you added a lot of analog functions since the analog functions don’t scale all that well. However, if you were adding a great deal of memory, then I think the die area dedicated to memory would impact the percent of die area utilized for the memory.
Does this impact the die area dedicated to the increasing number of IP blocks being used? I think it depends on the types of IP blocks we are talking about. You can put a lot of different IP blocks on an SoC. However, if we are talking about a 5-6 billion-transistor SoC, the IP blocks won’t take up all that much die area. An ARM CPU core at 400K gates comes to mind. You can put a lot of them on such a chip without having much impact on total die area. This is some of my thinking behind having such a chart. If I remember correctly, when the ITRS originally came out with this chart, they had memory equal to 94% of die area, re-used logic at 4% and new logic at 2%. Their thinking was that on 10 billion transistor chips, no one would have any time to put a lot of new logic on it. 2% of 10B is 200M. Back then no one was building even 100M transistor chips, so I think they felt that the overwhelming majority of such an SoC was going to be either memory or re-used logic. It is a lot easier to emplace memory and replicate it over and over than to spend time designing new logic gates.
I always felt this was a very short-sighted view of how designers were going to design their parts. Essentially it said that logic designers were going to become memory designers and this was never going to happen.
Looking forward
So, the real question becomes: is true innovation in hardware being constrained by how much logic can be designed or have we already reached the plateau of what can be reasonably added in a new design without raising risk to unacceptable levels? How big an impact will ESL have on that? Will it allow an increase in novelty without adding risk? Is the system architecture and verification becoming the bottleneck?
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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Udi.Barzilai
11/20/2012 9:37 AM EST
I honestly don't see the point in measuring the distribution of _die_area_ between new/reused design and memory.
Die area may influence cost models, yields etc but has little bearing on the design realted aspects of a chip.
One can fill 90% of a chip with replicated memory banks, using almost no design effort. Memory doesn't need to be functionally or formally verified. Doesn't need to be timing-closed. Doesn't need gate-level simulations. Integration of memory into a design is normally straightforward.
Memory should simply be left out of any discussion regarding "innovation in hardware being constrained".
Memory aside, we are left with new vs. reused blocks. Even here die area is of little value in the discussion, since if I have 12 hardened CPU cores replicated in my design, they may dominate the die area and still be a negligible part of the project when measured in design effort (= schedule, = investment, ~ innovation).
Just removing memories from the graphs in the article will show that while there is a clear increase in the die area share of reused designs, it is not a sharp exponential trend and the ratio just transitioned from ~40:60 to ~60:40 over 2 decades. This is by no means a _fundamental_ change of the industry.
Keeping in mind that due to replication, die area is at best an "inaccurate" indicator of design effort / innovation, I don't think any serious conclusion can be drawn about the subject purely from die-area data.
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