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EDA/IP weekly roundup – November 14th
Brian Bailey
11/14/2012 10:39 AM EST
This is a roundup of news or activities in the past few days that may be of interest to people.
X-FAB Silicon Foundries has announced its XT018, a trench dielectric isolated SOI foundry technology offering for 200V MOS capability at 180nm. Using the full dielectric isolation of this modular process allows blocks at different voltage levels to be integrated on a single chip instead of placed on different chips. The new technology combines fully isolated MOS transistors for the high-voltage drain with a 180nm technology for 1.8V / 5.0V I/O and up to 6 metal layers. Its process architecture utilizes a super-junction architecture with dielectric HV termination for the MOS transistors, allows compact design with a Ron as low as 0.3 Ωmm² for 100V and 1.1Ωmm² for 200V nMOS transistors.
Continuing its commitment to open source development, Mentor Graphics has announced the newest release of its Yocto Project™ 1.3-compatible Embedded Linux platform. This new Mentor Embedded Linux release is updated to include:
Berkeley Design Automation has announced Analog FastSPICE™ AMS (AFS AMS). AFS AMS combines Analog FastSPICE circuit simulator with any leading Verilog simulator to provide full Verilog-AMS language support. The tool’s configuration support enables arbitrarily nesting of Verilog-AMS, Verilog-D, Verilog-A, and leading SPICE netlist formats—all of which runs without translation.
Continuous developments in microelectronics are helping make advanced electronic braking systems (EBS) more reliable, responsive and affordable for mainstream vehicles. To enable the next generation of EBS and chassis control systems, Freescale Semiconductor and Continental have joined forces to design a high-performance, quad-core microcontroller (MCU) optimized for EBS applications. The two automotive suppliers are collaborating on a custom MCU program called Quad-core microcontroller for Automotive Safety And Reliability (QUASAR) designed to provide the processing intelligence for Continental’s next-generation EBS products. The first device in the family integrates four e200z4 cores based on Power Architecture® technology, making it the industry’s first quad-core automotive MCU with two pairs of cores in redundant lockstep.
Atrenta is the number two supplier of RTL power analysis tools according to the 2012 Market Trends Report published by Gary Smith EDA. The popular report on the EDA market shows Synopsys as the number one vendor in the segment with Atrenta leading the nearest competitor by seven percent. The report lists power analysis as one of the faster growing segments in the RTL market with a growth of 18 percent. Design complexity and the difficulty of moving power analysis to the system level were cited as reasons for the high growth. The relatively large impact that RTL analysis can have on power budgets was also mentioned.
Xilinx has announced its strategy for its 20nm portfolio, including the next-generation 8 series All Programmable FPGAs and second generation of 3D ICs and SoCs. The 20nm 8 series All Programmable FPGAs will provide 2x the performance, half the power, and 1.5 to 2x the integration capabilities over the current generation. High-growth applications for these devices include Nx100G wired networking, wireless L1 baseband co-processing for LTE A wireless networks, and next-generation system acceleration and connectivity. Xilinx's second generation 3D ICs will have homogeneous and heterogeneous configurations.
Altera and Northwest Logic have announced a 1,600 Mbps Reduced Latency DRAM (RLDRAM) 3 memory interface solution for use in its high-end 28 nm Stratix® V FPGAs. The RLDRAM 3 memory interface combines Altera’s auto-calibrated RLDRAM 3 UniPHY and Northwest Logic’s full-featured RLDRAM 3 controller core to significantly simplify interface design between RLDRAM 3 memory and the FPGA while maximizing memory throughput in high-end networking applications. This jointly-developed RLDRAM 3 memory interface solution has been hardware-validated in customer designs using Micron Technology’s RLDRAM 3 memories.
They have also announced a licensing structure that simplifies the integration of FPGA-based Industrial Ethernet designs in factory automation systems. Developed in collaboration with Softing Industrial Automation GmbH, the new licensing structure provides system developers with access to leading Industrial Ethernet protocols with no upfront license fees, no per-unit royalty reporting or protracted negotiations. Customers will have access to a variety of Industrial Ethernet protocols in a single Altera® FPGA, including PROFINET RT, PROFINET IRT, Ethernet/IP, Modbus TCP/IP, EtherNet/IP and PROFIBUS DP.
And to wrap it up they announced a new Motor Control Development Framework. The framework includes a set of customizable, single and multiaxis drive-on-a-chip reference designs and a portfolio of motor control hardware development boards, coupled with a system and software design methodology, to support the diverse requirements of next-generation drive systems.
Everspin Technologies continues its development of Spin-Torque Magnetoresistive RAM (ST-MRAM). ST-MRAM is a performance-optimized Storage Class Memory that provides non-volatility, high endurance and ultra-low latency. The 64Mb device is the first product in Everspin’s ST-MRAM roadmap that is planned to scale to gigabit density memories with faster speeds.
ANSYS has released version 14.5 of its multiphysics engineering simulation technology. In the real world, product performance varies by operating conditions, consumer usage, manufacturing processes and material properties. As products become increasingly complex, it is more challenging for engineers to fully understand the performance implications of design variations. Multiphysics simulation technology enables companies to make informed decisions based on insight gained from these analyses to deliver optimal results. ANSYS 14.5 delivers many new and critical multiphysics solutions, enhancements to pre-processing and meshing capabilities as well as a new parametric high-performance computing (HPC) licensing model to make design exploration more scalable.
Imperas has announced the Open Virtual Platforms model for the Renesas Electronics V850E PHO3 device. This virtual platform is available today from Imperas, and will soon be available from the OVP website (www.OVPworld.org). As with all OVP models, the V850E PHO3 virtual platform is available as an open source platform, but requires the OVPsim™ simulator to run.
Synopsys has announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer DFM Data Kit (DDK) encapsulated with Synopsys® Proteus mask synthesis technologies. The compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design. The TSMC 20-nm DDK complements traditional physical verification rules with a simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
X-FAB Silicon Foundries has announced its XT018, a trench dielectric isolated SOI foundry technology offering for 200V MOS capability at 180nm. Using the full dielectric isolation of this modular process allows blocks at different voltage levels to be integrated on a single chip instead of placed on different chips. The new technology combines fully isolated MOS transistors for the high-voltage drain with a 180nm technology for 1.8V / 5.0V I/O and up to 6 metal layers. Its process architecture utilizes a super-junction architecture with dielectric HV termination for the MOS transistors, allows compact design with a Ron as low as 0.3 Ωmm² for 100V and 1.1Ωmm² for 200V nMOS transistors.
Continuing its commitment to open source development, Mentor Graphics has announced the newest release of its Yocto Project™ 1.3-compatible Embedded Linux platform. This new Mentor Embedded Linux release is updated to include:
- New or enhanced software recipes incorporating the latest stable open source technology
- Improved compatibility with Yocto Project 1.3 compatible BSPs and software layers
- Compatibility with a broad range of ARM, MIPS, Power, and x86 core devices from semiconductor vendors such as Broadcom, Freescale, Intel, and Texas Instruments
Berkeley Design Automation has announced Analog FastSPICE™ AMS (AFS AMS). AFS AMS combines Analog FastSPICE circuit simulator with any leading Verilog simulator to provide full Verilog-AMS language support. The tool’s configuration support enables arbitrarily nesting of Verilog-AMS, Verilog-D, Verilog-A, and leading SPICE netlist formats—all of which runs without translation.
Continuous developments in microelectronics are helping make advanced electronic braking systems (EBS) more reliable, responsive and affordable for mainstream vehicles. To enable the next generation of EBS and chassis control systems, Freescale Semiconductor and Continental have joined forces to design a high-performance, quad-core microcontroller (MCU) optimized for EBS applications. The two automotive suppliers are collaborating on a custom MCU program called Quad-core microcontroller for Automotive Safety And Reliability (QUASAR) designed to provide the processing intelligence for Continental’s next-generation EBS products. The first device in the family integrates four e200z4 cores based on Power Architecture® technology, making it the industry’s first quad-core automotive MCU with two pairs of cores in redundant lockstep.
Atrenta is the number two supplier of RTL power analysis tools according to the 2012 Market Trends Report published by Gary Smith EDA. The popular report on the EDA market shows Synopsys as the number one vendor in the segment with Atrenta leading the nearest competitor by seven percent. The report lists power analysis as one of the faster growing segments in the RTL market with a growth of 18 percent. Design complexity and the difficulty of moving power analysis to the system level were cited as reasons for the high growth. The relatively large impact that RTL analysis can have on power budgets was also mentioned.
Xilinx has announced its strategy for its 20nm portfolio, including the next-generation 8 series All Programmable FPGAs and second generation of 3D ICs and SoCs. The 20nm 8 series All Programmable FPGAs will provide 2x the performance, half the power, and 1.5 to 2x the integration capabilities over the current generation. High-growth applications for these devices include Nx100G wired networking, wireless L1 baseband co-processing for LTE A wireless networks, and next-generation system acceleration and connectivity. Xilinx's second generation 3D ICs will have homogeneous and heterogeneous configurations.
Altera and Northwest Logic have announced a 1,600 Mbps Reduced Latency DRAM (RLDRAM) 3 memory interface solution for use in its high-end 28 nm Stratix® V FPGAs. The RLDRAM 3 memory interface combines Altera’s auto-calibrated RLDRAM 3 UniPHY and Northwest Logic’s full-featured RLDRAM 3 controller core to significantly simplify interface design between RLDRAM 3 memory and the FPGA while maximizing memory throughput in high-end networking applications. This jointly-developed RLDRAM 3 memory interface solution has been hardware-validated in customer designs using Micron Technology’s RLDRAM 3 memories.
They have also announced a licensing structure that simplifies the integration of FPGA-based Industrial Ethernet designs in factory automation systems. Developed in collaboration with Softing Industrial Automation GmbH, the new licensing structure provides system developers with access to leading Industrial Ethernet protocols with no upfront license fees, no per-unit royalty reporting or protracted negotiations. Customers will have access to a variety of Industrial Ethernet protocols in a single Altera® FPGA, including PROFINET RT, PROFINET IRT, Ethernet/IP, Modbus TCP/IP, EtherNet/IP and PROFIBUS DP.
And to wrap it up they announced a new Motor Control Development Framework. The framework includes a set of customizable, single and multiaxis drive-on-a-chip reference designs and a portfolio of motor control hardware development boards, coupled with a system and software design methodology, to support the diverse requirements of next-generation drive systems.
Everspin Technologies continues its development of Spin-Torque Magnetoresistive RAM (ST-MRAM). ST-MRAM is a performance-optimized Storage Class Memory that provides non-volatility, high endurance and ultra-low latency. The 64Mb device is the first product in Everspin’s ST-MRAM roadmap that is planned to scale to gigabit density memories with faster speeds.
ANSYS has released version 14.5 of its multiphysics engineering simulation technology. In the real world, product performance varies by operating conditions, consumer usage, manufacturing processes and material properties. As products become increasingly complex, it is more challenging for engineers to fully understand the performance implications of design variations. Multiphysics simulation technology enables companies to make informed decisions based on insight gained from these analyses to deliver optimal results. ANSYS 14.5 delivers many new and critical multiphysics solutions, enhancements to pre-processing and meshing capabilities as well as a new parametric high-performance computing (HPC) licensing model to make design exploration more scalable.
Imperas has announced the Open Virtual Platforms model for the Renesas Electronics V850E PHO3 device. This virtual platform is available today from Imperas, and will soon be available from the OVP website (www.OVPworld.org). As with all OVP models, the V850E PHO3 virtual platform is available as an open source platform, but requires the OVPsim™ simulator to run.
Synopsys has announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer DFM Data Kit (DDK) encapsulated with Synopsys® Proteus mask synthesis technologies. The compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design. The TSMC 20-nm DDK complements traditional physical verification rules with a simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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