There’s been lots of news lately on the industry transition to 450mm wafers. Recent headlines include coverage on the G450C’s 2015-16 target 10nm pilot line, TSMC’s $10B investment in 450nm, TSMC’s rollout delay from 2015 to 2018, and lithography being the big schedule bottleneck (yet again). The media have covered expectations of 400% higher starting wafer costs, a 20-50% increase in equipment costs, and fallout on the very health of the semiconductor equipment industry. There has also been some positive press too, including potential benefits at advanced nodes, such as 2.5x the number of die/wafer, and 20-25% less cost per die at 22nm and below.
What we have not heard much about is the impact to design engineers from the 450mm transition. Design and verification is, after all, what determines the content to enable all those high-volume, high-margin chips everyone is counting on to offset that huge transition expense. Yet there is little doubt that this change will have an impact, both on design methodology and on design flows – including EDA toolsets and even EDA standards.
There are a number of design and verification challenges impacted by a 450mm transition (either directly or indirectly). One prime example is design-centering and tighter process windows to handle increased inter-die / edge-to-edge wafer variation and additional edge defects. Since we are talking about process nodes in the range of 10nm, the variation problem on electrical performance will already be a huge concern. But when magnified by a much larger physical surface area (and composed of even thinner layers), variation in timing and power can be expected to increase and add even more pressure on design and verification. The impact could be felt across the industry by those involved with characterization, modeling, PDK development, EDA algorithms, and more. The way we will deal with that is through more advanced methodologies, models, and analysis tools. Methodologies for design centering will need to be more comprehensive and precise to ensure acceptable effective yield. This, in turn, implies more advanced standards to support these changes across the industry.
Running at 450mm will mean an accelerated trend towards fewer but larger, denser high-margin designs manufactured in high volumes. Accelerating the trend to larger die with more complex circuitry will further tax current EDA design tools, and the data exchange requirements between them. This means that verification methodology must somehow adapt to the practical limits on verification time with so much greater content and detail. This also means that our tool flow infrastructure must adapt to handle that much (10nm) detail and also that much more design content simultaneously. For example, the OpenAccess Coalition is already discussing a major enhancement to improve the accuracy of the coordinate system to greater than 32 bits, perhaps even going to 64 bits. This will need to be a well thought out change. There will be a number of downstream changes that must ripple throughout the EDA tool and standards world as the combination of increasing design content and detail stresses -- and even breaks -- many current tool flows.
Not yet mentioned is yet another change coming in the same time frame, exploiting the 450mm transition: 2.5D / 3D silicon design with through-silicon-vias (TSVs). The commercial use of 2.5D / 3D designs can benefit from a 450mm foundry infrastructure in several ways, and are expected to complement each other. However, there will nonetheless be additional challenges, and more changes required, to support both 450mm and 2.5D / 3D trends as a consequence.
What do you see coming as a design consequence of the 450mm transition? Please post your comments here on EDA Designline, and let’s have a discussion that can help us all prepare for these changes that can benefit the industry.
Steve Schulz, President and CEO, Si2
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