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A look back on 2012: Design tools and flows
Brian Bailey
12/18/2012 11:02 AM EST
This week, I have three segments of the 2012 retrospective. Today we look at those related to design tools and flows. Tomorrow will see verification and then conclude on Thursday with things related to semiconductor technology. That will wrap things up for 2012 and then it will be time to start seeing your predictions for 2013. Thanks again to everyone who contributed.
Shawn McCloud - VP of Marketing, Calypto
One of the main advantages of high level synthesis (SystemC or C++) is its ability to very quickly explore architecture alternative and see its impact on resulting RTL. Up until now, designers relied on pure experience or trial and error to optimize the RTL. At DAC 2012, Calypto announced Catapult LP, which is a first tool in the industry to incorporate power optimization and analysis technology directly in HLS, thereby generating power-ready RTL from the start. Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” of Catapult to seamlessly produce the lowest power RTL and optimize designs at the architecture level where 80% of power decisions are made. Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area (PPA) of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by also leveraging Calypto’s patented sequential analysis technology to deliver automatic fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings and is an industry first.
Sequential analysis has made a big different in reducing RTL power. Combinational clock gating has been the most popular power reduction technique in use for a long time. Combinational clock gating, if implemented efficiently can reduce dynamic power, but it still is limited in scope, because it does not cover various redundant activities that cause extraneous computations and wasted power. In these scenarios, writes done to a register are either unobservable down-stream or have the same value in consecutive cycles; i.e., they are redundant. Identifying these redundant writes requires multi-cycle analysis of the design and gating of the redundant writes. Such a gating condition is referred to as sequential clock gating. Calypto developed the patented sequential analysis which is able to reduce both static and dynamic power across multiple cycles. Customers have seen 60% reduction in power at RTL with sequential analysis.
Dr. Zhihong Liu - Executive Chairman, ProPlus Design Solutions
At 45nm and lower geometries including 28nm, yield is all but a crisis for process development engineers and circuit designers. The cause is a combination of increased random variations and layout-dependent effects, both having an impact on the chip yield. The solution is accurate yield prediction and realistic design optimization between performance and yield.
Modeling engineers must be able to accurately model these process effects in SPICE models that can be used during simulation and verification. Circuit designers then need a DFY toolkit for handling process variations with accurate SPICE models for process variations, a fast and reliable statistical simulation engine and hardware-validated sampling technologies.
Advances in accurate statistical modeling and design tools with high prediction accuracy and superior simulation performance are easing the problem. For example, ProPlus Design Solutions unveiled an integrated DFY product portfolio that includes advanced SPICE modeling, parallel SPICE simulation and statistical analysis. The tools offer a look at how different variation effects can be accurately modeled and properly used in circuit analysis, and how efficiently yield analysis can be done in two different areas. The two areas are regular 3-sigma Monte Carlo runs for analog circuit designs and special High Sigma runs such as 5~6 sigma for memory and standard cell designs.
Mike Gianfagna - Vice President of Corporate Marketing, Atrenta Inc.
We launched a new version of our IP Kit with TSMC. We're delighted with the way that program is growing. ARM's recent announcement to join is a good example of the progress being made.
Shawn McCloud - VP of Marketing, Calypto
One of the main advantages of high level synthesis (SystemC or C++) is its ability to very quickly explore architecture alternative and see its impact on resulting RTL. Up until now, designers relied on pure experience or trial and error to optimize the RTL. At DAC 2012, Calypto announced Catapult LP, which is a first tool in the industry to incorporate power optimization and analysis technology directly in HLS, thereby generating power-ready RTL from the start. Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” of Catapult to seamlessly produce the lowest power RTL and optimize designs at the architecture level where 80% of power decisions are made. Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area (PPA) of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by also leveraging Calypto’s patented sequential analysis technology to deliver automatic fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings and is an industry first.
Sequential analysis has made a big different in reducing RTL power. Combinational clock gating has been the most popular power reduction technique in use for a long time. Combinational clock gating, if implemented efficiently can reduce dynamic power, but it still is limited in scope, because it does not cover various redundant activities that cause extraneous computations and wasted power. In these scenarios, writes done to a register are either unobservable down-stream or have the same value in consecutive cycles; i.e., they are redundant. Identifying these redundant writes requires multi-cycle analysis of the design and gating of the redundant writes. Such a gating condition is referred to as sequential clock gating. Calypto developed the patented sequential analysis which is able to reduce both static and dynamic power across multiple cycles. Customers have seen 60% reduction in power at RTL with sequential analysis.
Dr. Zhihong Liu - Executive Chairman, ProPlus Design Solutions
At 45nm and lower geometries including 28nm, yield is all but a crisis for process development engineers and circuit designers. The cause is a combination of increased random variations and layout-dependent effects, both having an impact on the chip yield. The solution is accurate yield prediction and realistic design optimization between performance and yield.
Modeling engineers must be able to accurately model these process effects in SPICE models that can be used during simulation and verification. Circuit designers then need a DFY toolkit for handling process variations with accurate SPICE models for process variations, a fast and reliable statistical simulation engine and hardware-validated sampling technologies.
Advances in accurate statistical modeling and design tools with high prediction accuracy and superior simulation performance are easing the problem. For example, ProPlus Design Solutions unveiled an integrated DFY product portfolio that includes advanced SPICE modeling, parallel SPICE simulation and statistical analysis. The tools offer a look at how different variation effects can be accurately modeled and properly used in circuit analysis, and how efficiently yield analysis can be done in two different areas. The two areas are regular 3-sigma Monte Carlo runs for analog circuit designs and special High Sigma runs such as 5~6 sigma for memory and standard cell designs.
Mike Gianfagna - Vice President of Corporate Marketing, Atrenta Inc.
We launched a new version of our IP Kit with TSMC. We're delighted with the way that program is growing. ARM's recent announcement to join is a good example of the progress being made.
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