This week, I have three segments of the 2012 retrospective. Yesterday we looked at those related to design tools and flows. Today will see verification and then conclude on Thursday with things related to semiconductor technology. That will wrap things up for 2012 and then it will be time to start seeing your predictions for 2013.
Bill Neifert - Chief Technology Officer, Carbon Design Systems
The Carbon Performance Analysis Kit (CPAK) family to accelerate SoC performance analysis, optimization and verification was unveiled midyear. Each CPAK contains reference hardware and software designs along with analysis and debug software for a specific IP block.
Dr. Raik Brinkmann - President and Chief Executive Officer - OneSpin Solutions
Design teams are relying more heavily of silicon intellectual property (IP) blocks for SoC designs for any number of reasons, from budgetary and project schedules to productivity. This phenomenon is welcome, but creates a new concern: the quality of the original verification of that piece of IP. At OneSpin, we have developed a formal metric-driven verification (MDV) methodology and technologies to eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics.
Adnan Hamid - Chief Executive Officer, Breker Verification Systems
A common misperception is that the SoC will work as intended if the IP blocks on the chip have been well verified. Fortunately, SoC development teams are learning from their mistakes and adopting Breker’s TrekSoC verification solution. TrekSoC automatically generates self-verifying C tests cases running on the SoC’s embedded processors to verify the complete design. Graph-based scenario models of the chip’s data flow fuel the generation process. This approach is complementary to the testbench-based approach adopted for the IP blocks and leverages existing verification components.
An ongoing trend comes from the consumer electronics market segment driving the creation of SoCs with multiple embedded processors for enhanced product functionality and performance. In 2012, Breker announced support for these types of SoC designs –– a major accomplishment. TrekSoC automatically generates multi-threaded test cases for SoC designs with multiple heterogeneous embedded processors, providing effective verification between stitching and shipping.
Oz Levia - Vice President of Marketing and Business Development and Corporate Counsel, Jasper Design Automation
We expanded into new and emerging verification areas, providing users with the ability to apply formal methods to even more verification challenges and domains and the industry has validated Jasper's business model by adopting the new Apps product packaging.
Mike Gianfagna - Vice President of Corporate Marketing, Atrenta Inc.
We successfully acquired NextOp Software (BugScope product) and the integration into Atrenta is going quite well. Our goal is to build a broad platform that covers both design and verification optimization at RTL, and we're well on our way toward that goal.
Andreas Veneris - Chief Executive Officer, Vennsa Technologies
was the year that functional debugging received the recognition it
deserves. As a central theme of this year’s DAC, the community spoke
loudly about the need to solve a problem that manifests itself in every
aspect of verification. Evidently, this awareness creates an opportunity
for novel debugging features in existing tools to differentiate them,
generate incremental revenue and for the development of new stand-alone
products. Vennsa’s OnPoint is one of those software tools.
It automates debugging and error localization and is being adopted by
engineering teams worldwide.
First, Synopsys acquiring
SpringSoft, then Synopsys immediately filed a countersuit against
Mentor, after acquiring EVE. Don’t think anyone saw these things coming!