A look back on 2012 - Verification

12/19/2012 10:25 AM EST

Chi-Ping Hsu, Senior VP, R&D, Silicon Realization Group, Cadence Design Systems, Inc.

In the verification arena, this year has seen continued rapid adoption of our Universal Verification Methodology (UVM), Verification IP (VIP), and emulation technologies. As a driving company in these areas, Cadence has made significant contributions to the progress of the industry.

John Chilton - senior vice president, marketing and strategic development, Synopsys

The design flow has changed greatly over the past few years, including the adoption of SystemVerilog, UVM, broad use of IP and VIP and more emulation. SystemVerilog and UVM give us a consistent language and methodology, which is important when companies are exchanging verification IP. Transaction-level modeling is becoming standard practice at many companies to accelerate software availability. UVM, SystemVerilog and TLM provide a very solid foundation of interoperable standards for verification, and a lot of that came about in 2012.

Mentor Graphics

Formal

The Questa Verification Platform was enhanced to deliver a wide spectrum of formal applications that range from fully automatic formal checking that everyone can easily use, to property checking with custom coded assertions for advanced users. The latest addition to the platform is Questa CoverCheck, which accelerates the process of code coverage closure.  Code coverage closure typically involves many engineering weeks of effort to manually review code coverage holes to determine if they can be safely ignored and if not, to generate hand-crafted simulation tests to cover them. Questa CoverCheck makes it easy for non-expert users to leverage formal methods to complete this process by automatically identifying the set of reachable and unreachable coverage bins. Consequently, it significantly reduces the time required for code coverage sign-off, bringing predictability to the schedule. CoverCheck also ensures higher design quality by preventing bugs from slipping through the verification process due to mistakenly ignored code coverage bins Questa Formal also includes AutoCheck technology, which automatically analyzes the RTL design and synthesizes assertions that are then processed by powerful formal engines to check for correct sequential design behavior. This allows designs to be easily verified as free from common functional errors without the need to write a testbench or any assertions.

UVM

Mentor continued our UVM leadership in 2012 by facilitating wider adoption of UVM both through tools and through education. The Questa Verification Platform features full UVM support, including Questa inFact’s intelligent testbench automation, which generates advanced UVM sequences to target coverage more effectively.

We also released two UVM-related solutions to encourage its adoption. UVM Express provides guidelines for incrementally adopting UVM to improve legacy testbenches, and UVM Connect provides transaction-level connectivity between UVM and SystemC TLM-based designs. UVM Connect also allows SystemC components to be used as components inside a UVM testbench, allowing users to take advantage of the strengths of either language for different parts of their verification environment. Video training and examples for each of these solutions are included in our Verification Academy online learning website, along with a new “Advanced UVM” module that includes 10 in-depth videos about how to use UVM effectively. The Verification Academy is the most comprehensive online resource for Verification training with 13,000 members and growing

Coverage

More verification engineers using the Questa platform are now achieving their functional coverage goals 10X faster than with other simulation tools, by taking advantage of three unique technologies that are integrated into the Questa platform.  First, Questa Verification Management enables ease of defining and modeling coverage goals, and automation of tracking, analyzing, and reporting coverage results.  It is based on the Questa Unified Coverage Database (UCDB), whose API formed the basis of the Unified Coverage Interface Standard (UCIS) adopted by Accellera earlier this year.  Second, the Questa Verification IP (VIP) portfolio of bus protocols, peripherals, and interfaces now includes the latest AXI ACE 4 protocol with built in Cache Coherent Interconnect Monitors (CCIM).  Like all of the Questa VIP models, it includes comprehensive built-in testplans and coverage models, as well as extensive stimulus and checks, to ensure achieving the highest levels of protocol coverage.  Third, Questa Intelligent Testbench Automation (iTBA) reduces the time spent writing testbenches by 50% or more, achieves functional coverage targets >10X faster, and lets teams expand coverage goals even further.  This year Questa iTBA has been expanded to support software driven verification at the SoC level in addition to SystemVerilog driven testing at the RTL level.

Low Power Verification

Mentor has taken another leap forward in capabilities and leadership in Low Power Verification.  We are a key contributor and have taken a leading role driving the 2.1 version of the IEEE 1801(UPF) low power standard which is in the process of ratification.  The Questa Platform continues to have both the leading support for UPF and unique capabilities to automatically analyze, visualize and debug the UPF defined power intent all in a high performance native Questa Simulation implementation.  Additionally, the Mentor Veloce emulation and acceleration platform now supports the same UPF enabling a unified Low Power verification solution that can build from block to system and take a design from simulation through emulation to verify the power intent of the largest and most complex designs.