Predictions for 2013 – EDA/IP

1/10/2013 10:35 AM EST

Michiel Ligthart - president and COO, Verific Design Automation

Semiconductor IP management and integration within a design flow has become more and more prevalent. As semiconductor companies cannot find off the shelf tools that fit their needs, they will develop these tools themselves. The trend will continue through 2013.

Ken Karnofsky - senior strategist for signal processing applications, MathWorks

Engineers will increasingly rely on tools to model and simulate smart devices and systems using methods that span traditional engineering disciplines, and will base their development process on those system models. Leading companies already use these methods to optimize design choices, improve collaboration across development teams, and eliminate waste in their development process.

Brad Quinton - chief architect, Tektronix

FPGA based verification technologies:  ASIC Prototyping, emulation, etc. will become much more capable in a large part because of the extremely large capacity of the Virtex-7 2000T FPGA.  In a different direction, SystemVerilog will be considered completely mainstream and users will no longer distinguish between Verilog and SystemVerilog, and SystemVerilog will become "Verilog".

Dr. Raik Brinkmann - President and Chief Executive Officer, OneSpin Solutions

In 2013, the focus by the electronics and EDA community will remain on verification, which may not be surprising given how much of a project schedule is set aside for verification.

Proper functional verification is becoming a matter of life and death, especially when SoCs are part of safety critical applications, such as steer-by-wire or other driver-assisted systems. Verification must not only be seen as a means to save cost by saving respins or mask sets, or improving time-to-market. It should be viewed as the way to ensure design correctness. No one can afford bugs in the field any longer, even if the device is reprogrammable. Any safety-critical SoC will have to rely on thorough verification of individual blocks, their integration as well as on trustworthy flows into silicon.

As a result, state-of-the-art verification technologies typical for ASIC SoC design flows will be adopted by the FPGA community. Formal technologies, such as formal assertion-based verification and formal logic and sequential equivalence checking, will become as important in the FPGA segment as they are already in the ASIC world.

Let’s not overlook ASICs. The complexity of ASIC designs will continue into 2013 and beyond and will need as much functional verification coverage as before. In fact, it may need even more.

Andreas Veneris - Chief Executive Officer, Vennsa Technologies

I do foresee solid growth in the debug sector. 2012 was the year of “debug amalgamation” where the EDA community publicly acknowledged that on the flip side of the verification burden, there is fast-growing debug pain. Being an emerging sector of significant market value size, debugging today offers tangible opportunities for novel, standalone solutions to present alternatives and promote competition. It also offers opportunities for companies to add vertical solutions to existing product lines to generate incremental revenues and for product differentiation.

2013 may be a tough year for the global economy if the Oracle is true, but the verification and debug space within EDA will continue to be strong.

Marc Serughetti - Director of Business Development, System Level Solutions, Synopsys

The Virtual Prototyping tool market will be evolving along two major areas

• The first area is a more traditional modeling toolset with IP model libraries, these tools will continue to evolve toward making the creation of virtual prototype easier and faster. This includes making IP model library more widely available, continuous simulator performance improvement, etc …
• The second area is the out of the box virtual prototyping solution for software developer (VDKs with pre built virtual prototypes), we will see more VDKs becoming available which can be directly used by software developers without requiring any modeling effort. Virtual Prototyping becoming a software tools (rather than an EDA like modeling tool only)

As a result we will see an increase in integration of virtual prototypes with other technologies. In particular:

• Simulation of system will be expanding to be more representative of a complete system including digital hardware, software, analog, mechanical system, so we will see more integration starting to happen between different domain simulators.
• More integration with tools participating in the software development tool flow will appear.

We will also start to see the emergence of more post silicon use cases. These use cases may be more prominent in some markets, for example fault and coverage testing in safety critical application.

Michael Sanie - Director of Verification Product Marketing, Synopsys

SoCs are growing in unprecedented complexity, combining multi-processors, cache-coherence, sophisticated interface protocols, advanced low power techniques and embedded software. In 2013, the industry will explore new levels of verification integration and productivity.  Building on what the industry has already achieved with SystemVerilog, UVM, next-generation verification IP, native low power simulation and other advancements, SoC design and verification teams will continue to increase their use of complex testbenches, coverage planning and management, and debug for their block and subsystem-level verification.  In order to achieve even higher levels of productivity, project teams must move beyond block and subsystem verification and focus more on full SoC verification. To enable this emphasis, expect simulation, acceleration, emulation, formal and debug technologies will begin to integrate in new ways.

Performance, capacity and debug will continue to pose the largest challenges for the verification of complex SoCs.  Market and competitive pressures, however, are adding a new challenge into the verification mix:  managing verification schedule and its predictability.  To manage resources, cost and schedule, project teams must now employ a number of verification technologies, all critical to completion of the overall mission.  2013 will mark the beginning of a transition to a super-platform of these technologies combined with unified coverage planning and management, as well as unified debug. Not only will this platform allow these relatively discrete verification technologies to work together and offer higher productivity, but it will also enable seamless and efficient transitions from one technology to another and back again, thereby making verification schedules much more manageable and predictable.

Prasad Paranjpe - Galaxy Platform Marketing Manager, Synopsys

All of the new physical characteristics can be optimized only if EDA software is aware of all the physical ramifications. This will require even closer collaboration with both customers and foundries to implement practical working flows.

Physical awareness across traditional boundaries results in several benefits throughout the flow. In the past, your phone and calendar were physically separate. Now that both are in a single device your phone does not need to ring if you are in a meeting.  In a similar manner a single integrated implementation system can and should be aware of manufacturing constraints or DRC limitations and be able to use the same database to ensure that placement and routing will match foundry rules. The same technology saves time during an ECO not only by making sure that any changes conform to the rules but also by limiting the analysis to the affected region. Conversely, on the front end, RTL designers can provide initial floor plan constraints and placement to seed place and route tools while the placer or router can provide more detailed results that can be used to synthesize more efficient logic. More designers will take advantage of integrated flows such as In-Design physical verification.

Design costs that meet these goals will climb even higher in 2013. By implication, any successful design will require large production volumes in order to be cost effective. Designers will need to spin multiple designs from the same basic IP that serve more than one market with varying power/performance profiles. There are more than enough transistors on an SoC to handle almost any compute task. It is a matter of what performance for a given amount of power. These multiple designs could be hard re-spins or handled in software with different profiles or architecturally woven into the system.

All of drivers point to an even closer collaboration between the EDA industry, foundries, and design teams to deliver working flows which span the range from initial design all the way through to manufacturing, test and packaging.

Cary Chin, director of technical marketing, low power solutions, Synopsys

• IC – big move to FinFET configurations for lower power and higher performance
• Tools gradually move toward low power “understanding” rather than just low power “aware”