ICScape, Calypto, Cadence, Forte, Solido and IC Manage
Ravi Ravikumar - Vice President Marketing, ICScape Inc.
on all the early productization work that has gone into the creation of
20nm test chips and flow, it is clear that a tighter EDA-foundry-design
information exchange loop will be required to create successful
This tighter information exchange loop calls for
add-on EDA capabilities – like increased model accuracy, double
pattering/coloring, handling of DFM/litho/DFY issues, and larger data
sizes – thereby creating a point of disruption at 28nm.
will also be the year when distinct sub-28nm tools, flows and deployment
models begin to emerge, which will monetize the cost of add-on
Shawn McCloud - V.P. Marketing, Calypto Design Systems
consideration will become critical not only for mobile applications but
also for plugged-in devices as the cost of power consumption and
cooling is getting prohibitive. Designing for Power will play a bigger
role at 28nm as thermal and supply integrity force engineers to design
for low power earlier in the design cycle. Porting legacy RTL to smaller
technology nodes means more designers will opt for automatic
optimization and let the tool do the power optimization for them.
Automatic power optimization tools will become a precursor to synthesis
and in fact, there will be a need for tighter collaboration between RTL
power optimization and logic synthesis tools.
Lip Bu Tan – CEO, Cadence
need for mixed-signal design capabilities will broaden as more SoCs
integrate analog functionality for both traditional user interfaces and
high-speed data interfaces. Low-power design will be essential for
mobile devices and large data centers. The pressure for performance and
functionality will lead semiconductor companies to move to advanced
process nodes, including 14nm FinFET technology, and this will require
improvements to design tools and flows along with deep collaboration
throughout the semiconductor design ecosystem.
Designers will be
faced with increasingly complex chips and systems, but time-to-market
pressures will not ease. This will drive EDA tools to support higher
levels of abstraction and to facilitate hardware/software
co-development. Functional verification tools and methodologies will
need to handle large mixed-signal SOCs.
And the growing use of third-party IP will place increasing demands on IP verification methodologies and support.
Brett Cline - VP of Marketing and Sales, Forte Design Systems
reuse has long promised great productivity benefits. However, the
functionality of the existing design rarely is exactly the same as the
specification for the new design. Add in new process technologies, clock
speeds, and quality metrics and witness the quick demise of a well
laid-out RTL reuse plan.
The trend toward higher levels of
abstraction will push further into IP development in 2013 because the
cost of creating, verifying and maintaining hardware blocks as RTL code
is prohibitive. Designs modeled at higher levels of abstraction are
easier to develop and maintain, making functional IP reuse much easier.
When combined with high-level synthesis, these models can be retargeted
to new process nodes to meet more aggressive performance targets. Most
important, designs can be optimized quickly for area, power, and
performance from a single source –– something just not possible with RTL
Design teams worldwide continue to be concerned about
power management, power efficiency and low-power design. The EDA
industry will unveil new power-reduction tools in 2013 and higher-level
power optimization strategies will continue to gain steam.
Trent McConaghy - CTO and co-founder, Solido Design Automation
moving to handle double patterning parasitics, FinFET model sets that
go beyond fast fast / slow slow corners, more power modes, more loads,
and more parasitics, will cause PVT corner count to go from a dozen, to
10^3 to 10^6 corners. Bleeding-edge designers have already discovered
this issue. In response, tools that can perform fast, trustworthy
verification across 10^3 to 10^6 corners will become mainstream, as they
get mandated into signoff flows. Mismatch-aware design will become more
widespread and less ad-hoc, as designers learn to leverage tools that
allow them to continue doing corner-based design (but now with corners
that include local variation).
Statistically-aware memory design
at the array level will also become more widespread to better connect
chip-level tradeoffs with cell-level design. Post-silicon calibration
and trimming have been around a while to help manage variation, but its
complexity has grown literally exponentially, and ad-hoc methodologies
are starting to break. Thus methodologies that reconcile calibration and
variation-aware design in a more rigorous fashion will become more
Finally, since this all requires simulation, the
simulation wars will continue to be hot, but the lynchpin will be in the
smart selection and management of simulations by task-oriented
variation design tools.
Shiv Sikand - co-founder and VP engineering, IC Manage
When IP blocks are distributed and reused, they change in an
incremental fashion. Dependency management is needed for communication
through this space of IP derivatives. By retaining and encapsulating the
relevant properties, bug information, and design history with the IP,
these attributes can then be propagated throughout the IP's of versions
across the design and design derivatives across the enterprise. For
example, with today’s complexities, the context of where the IP is used
in a design can be nearly as important as the IP itself; you cannot
expect an IP placed at one design location to necessarily behave
identically to the same IP placed elsewhere. Thus companies must ensure
they have the infrastructure to promptly communicate such newly
discovered information about the IP, such as general bugs and when the
IP doesn't function as expected under a certain condition.
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