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Hogan says retooling underway for custom 2.0
James Hogan
1/11/2013 11:53 AM EST
Custom 2.0 3D transistors - Bring simulation modeling challenges
A FinFET transistor is a 3D structure; the structure rises above the planar substrate and has more volume than a planar gate for the same planar area. A FinFET transistor has much lower leakage current, but also has significantly more complexity both in manufacturing and design. We had Intel’s trigate FinFET at 22 nm in 2012. In 2014, we will have ultra-thin body, fully depleted SOIs (silicon-on-insulators) at 14 nm, a complementary “3D” technology, to help reduce leakage.
3D FETs will be prominent in the next ten years, but device engineers and circuit engineers do not have the numerous years of experience that they have with 2D (planar) devices. The 3D nature of FinFET devices and the multiple fins making up the transistors introduce a large number of new parasitic resistances and capacitances to be considered in extraction, modeling, and simulation. Higher model complexity is required with many more equations. These have all been standardized in the BSIM-CMG compact models, which are used by BDA's Analog FastSPICE, Cadence's Spectre, and Synopsys' HSPICE simulators to validate circuit designs using these new BSIM-CMG models.
Intel, IBM, TSMC and Samsung offer very different 3D transistors at the various process nodes. The manufacturing challenges are considerable, and Intel has certainly led the world in this capability. It is not clear (to me at least) who will be able to stay in the foundry game going forward.
A FinFET transistor is a 3D structure; the structure rises above the planar substrate and has more volume than a planar gate for the same planar area. A FinFET transistor has much lower leakage current, but also has significantly more complexity both in manufacturing and design. We had Intel’s trigate FinFET at 22 nm in 2012. In 2014, we will have ultra-thin body, fully depleted SOIs (silicon-on-insulators) at 14 nm, a complementary “3D” technology, to help reduce leakage.
3D FETs will be prominent in the next ten years, but device engineers and circuit engineers do not have the numerous years of experience that they have with 2D (planar) devices. The 3D nature of FinFET devices and the multiple fins making up the transistors introduce a large number of new parasitic resistances and capacitances to be considered in extraction, modeling, and simulation. Higher model complexity is required with many more equations. These have all been standardized in the BSIM-CMG compact models, which are used by BDA's Analog FastSPICE, Cadence's Spectre, and Synopsys' HSPICE simulators to validate circuit designs using these new BSIM-CMG models.
Intel, IBM, TSMC and Samsung offer very different 3D transistors at the various process nodes. The manufacturing challenges are considerable, and Intel has certainly led the world in this capability. It is not clear (to me at least) who will be able to stay in the foundry game going forward.
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