EDA/IP weekly roundup – January 30th 2013

1/30/2013 11:28 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Semico recently released their Quarterly Wafer Demand Summary and Data, and as usual, there is good news and bad news.  The good news is, manufacturing yields on 28nm have improved so for the time being, capacity is no longer a constraint in the supply chain.  The bad news is, while holiday sales started off on a high note, they were unable to sustain the growth through the end of the year.  Semico believes the slow holiday season, along with a drop in consumer confidence, has encouraged the electronics supply chain to continue to maintain conservative inventories.

Real Intent has a new release of its Meridian Constraints product for design constraint management. This new software release adds enhanced speed, analysis and SystemVerilog language support including:

• Constraints equivalency checks for top-level versus block-level of design to ensure that block-level constraints have been aggregated correctly in the complete design, or that constraints are correctly propagated downward for individual block verification
• An enhanced timing exceptions verification engine with greater speed and coverage
• Significant enhancements to the SystemVerilog support and associated error handling
• Verdi3 integration - the industry-leading debug platform from Synopsys (formerly SpringSoft)

ProPlus Design is shipping 9812D, the latest generation wafer-level, 1/f noise measurement system, to select customers. Leading wafer fabrication facilities use 7*24 1/f noise measurement data to assess process quality. A three-to-10X throughput improvement of the 9812D system means faster data collection and early detection of process issues, which if undetected, could result in significant financial losses. The 9812D increases return on investment by integrating DSA, eliminating the need for expensive external signal processing equipment. This reduces the up-front investment, set-up risk and time. The 9812D low-frequency 1/f noise measurement system is designed to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), diodes and diffusion resistors. In addition to frequency domain measurement, 9812D can measure device noise in the time domain and can be used to perform on-wafer auto measurement for flicker (1/f) noise and Radom Telegraph Signal (RTS) analyses.

S2C has added 13 new Prototype Ready interface cards and accessories to its library of pre-engineered hardware and software components aimed at accelerating the development of SoC prototypes. These new modules enable users to prototype SoC designs with a variety of interfaces such as PCIe, Gigabit Ethernet, HDMI, LCD and Dual A9 ARM Processor, and work out-of-box with the new S2C's Virtex-7 TAI Logic Module Series Rapid SoC/ASIC Prototyping Platform. These pre-engineered solutions enable users to focus on SoC prototype development rather than create solutions all over again that have been engineered and verified by S2C.

Cadence has announced the availability of Virtuoso® Advanced Node, a new set of custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below. Built on the Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today's leading consumer electronics devices.

EnSilica and Phoenix Systems have ported the Phoenix-RTOS, designed specifically for both single and multicore embedded systems applications, to the eSi-RISC family of configurable soft processor cores. The collaboration between EnSilica and Phoenix Systems further expands the eSi-RISC ecosystem with an embedded RTOS capable of fully utilizing eSi-RISC’s hardware MMU with memory protection and security features such as data execution protection. It also paves the way for embedded power line and wireless smart grid solutions with the combination of Phoenix Systems’ proposed smart grid software protocol stacks and eSi-RISC’s support for custom instructions accelerating performance and improving PHY layer implementations.

Verific Design Automation ended 2012 with 52 active user companies and a revenue increase of 20% over 2011. In 2012, Verific signed six new licensed customers in a mix that includes both electronic design automation (EDA) companies and integrated device manufacturers (IDMs). Several existing customers added further software to their existing product mix. Verific’s software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs.

Real Intent has new releases of its Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools for early functional analysis of digital designs. Ascent products find bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation. New Ascent IIV features include faster performance on designs greater than 100K gates, incremental runs, a new double-toggle net check and VCD traces that provide a marker to show the time of failure. New features in Ascent XV for detecting unknowns in digital hardware include, enhanced modeling of X’s that come from retention flops, broader coverage in identifying all X-sources and X-sensitive logic, tighter SimPortal integration and a new debug interface that shows the path from the sensitive construct to an X-source, facilitates waivers of X-sources and X-sensitive nets, and provides links for source code navigation.

Synopsys has announced availability of its multiprotocol DesignWare® Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express® (PCIe®) 3.0 and 10GBASE-KR. The new DesignWare IP implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet.

Mentor Graphics has announced the newest release of its HyperLynx® product for high-speed design and analysis. Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster. Engineers and designers who use the HyperLynx products during the system design process can analyze potential high-speed design issues that can impact signal integrity, power integrity, and electromagnetic interference (EMI) performance.

Kilopass Technology and Semiconductor Manufacturing International Corporation have announced that Kilopass IP has successfully completed the JEDEC 3-lot qualification for the SMIC 65nm, 55nm and 40nm low-leakage (LL) CMOS process technologies. Kilopass provides designers tamper-resistant, highly reliable NVM IP based on SMIC’s processes. JEDEC qualification assures designers that Kilopass IP used to store mixed-signal trim data, boot code, and security keys for application processors, MCUs and RF transceivers will guarantee operation and data retention for over 10 years.

Oasys Design Systems has announced that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required for design closure. RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues. The introduction of RealTime Explorer by Oasys enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts.