EDA/IP weekly roundup – February 13th 2013

2/13/2013 1:03 PM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Synopsys has a new release of its FineSim™ circuit simulator. The 2012.12 release of FineSim introduces new algorithms for layout resistance and capacitance (RC) parasitic reduction and complex on-chip power network simulation, enabling up to 2X simulation speed-up and capacity for post-layout simulation of a broad range of memory designs compared to previous versions of FineSim. In addition, this release of FineSim incorporates the industry-proven HSPICE® device modeling engine, which includes support for the FinFET BSIM-CMG 106.1 standard. The new built-in HSPICE modeling engine ensures that FineSim simulation results are consistent with HSPICE golden accuracy simulations.

Synopsys reports that United Microelectronics Corporation (UMC) has selected Synopsys' IC Validator physical verification product for lithography hot-spot checking at the 28-nm process node. As part of Synopsys' Galaxy™ Implementation Platform, IC Validator is an add-on to Synopsys' IC Compiler™ solution for In-Design physical verification, enabling place-and-route engineers to accelerate time to tapeout by preventing late-stage surprises and minimizing manual fixes. IC Validator pattern matching extends the In-Design flow with automatic repair of lithography violations.

Fujitsu and Panasonic have signed a memorandum of understanding to consolidate the design and development functions of the system LSI businesses of Panasonic and Fujitsu Semiconductor Limited. With the backing of capital contributions from third-party investors, Fujitsu and Panasonic will establish a new company under a fabless business model, enabling LSI design and development functions. At the same time, the two companies have agreed to discuss the transfer of business to the new company.

Cadence intends to acquire Cosmic Circuits, a provider of analog and mixed-signal intellectual property cores. Cosmic Circuits offers silicon-proven IP solutions in connectivity and advanced mixed-signal technologies in the 40nm and 28nm process nodes, with 20nm and FinFET development well underway.

Calypto Design Systems and Real Intent have integrated Calypto’s Catapult high-level synthesis tool and Real Intent’s Ascent™ Lint product. The resulting solution ensures Catapult-generated RTL code is lint clean and error free for a safe and reliable implementation flow from RTL to GDSII layout.

Cadence  has elected Young K. Sohn, president and chief strategy officer of Samsung Electronics to its board of directors. Mr. Sohn brings industry, financial, operational and governance expertise to Cadence through his experience in executive leadership at leading semiconductor firms and advisory roles in investment firms. The company also announced the retirement of Donald L. Lucas from the board.

Tanner EDA has integrated the DesignCraft™ and TimeCraft™ digital design tools from Incentia Design Systems into Tanner EDA’s HiPer Silicon AMS solution. DesignCraft is Incentia's logic synthesis tool with integrated capability to synthesize and optimize for area, power, timing, and design-for-testability (DFT). TimeCraft is Incentia's static timing analyzer (STA) for nanometer timing analysis and sign-off. HiPer Silicon AMS extends Tanner EDA’s design, layout and verification toolset to include tools for design entry, simulation, debugging, static timing and synthesis for digital circuits.

OneSpin Solutions is bundling multiple verification tools into its new OneSpin 360™ DV Product Family. OneSpin 360 DV is shipping now and contains three separate verification tools for push-button formal analysis, automated transaction-level ABV and functional coverage. Tools come bundled with pre-packaged solutions at no additional charge.

OneSpin has also announced availability of 360™ EC-RTL, equivalence checking software that compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. An RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code, it features register, sequential and power optimization verification.

Imperas has announced that its models and tools have found two Linux bugs. Using an ARM processor core (Cortex-A15), an Imperas customer isolated a bug in Linaro Linux. This was caused by incorrect hypervisor mode change that could result in unpredictable behavior. The Imperas Verification, Analysis and Profiling (VAP) tools, combined with the company's 3-D debug technology, were used to isolate another bug in a customer-specific version of Linux. This complex bug was detected within about two days of the first Linux boot on the virtual platform.

Imperas also announced availability of OVP models for the ARM Cortex–A15 MP family. The new models have the usual OVP characteristics: - 100s of millions of instructions per second performance - Native interfaces for OVP C and SystemC/TLM-2.0 virtual platforms - Working with OVPsim, software running on these models can be debugged using GDB and Eclipse.

Forte Design Systems has announced its Cynthesizer™ high-level synthesis (HLS) is now supporting IEEE 1666™-2011 SystemC. The latest version of Cynthesizer supports the new SystemC syntax for asynchronous resets. The new language support for reset semantics in SC_THREADs allows hardware designers to implement synthesizable designs using the same process construct commonly used for transaction-level system modeling. The result is improved interoperability between models used for implementation, system modeling and hardware/software co-design. In addition to these synthesis-related benefits, use of IEEE 1666-2011 SystemC gives Cynthesizer users access to process control extensions for modeling embedded software systems, the integrated TLM-2.0 library and features for pausing and restarting simulation.

High-speed serdes (serializer/deserializer) links on printed circuit boards (PCB) sometimes don’t achieve their expected throughput rates because of process variances in manufacturing. A new e-book from ASSET® InterTech explains the defects caused by process variances and how they can be detected with minimum effects on the manufacturing line. Entitled “How to avoid poor serdes performance caused by circuit board manufacturing variances”, the new e-book includes a case study which analyzes the effects of manufacturing variances on a typical serdes trace on a PCB. A tool also included in the e-book can be used by engineers to calculate resistance and impedance on transmission lines. The e-book is available now on the ASSET web site at: http://www.asset-intertech.com/Products/High-Speed-I-O-Validation/HSIO-Software/Manufacturing-Variance-e-Book