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Anyone for a free breakfast next week?
Brian Bailey
2/22/2013 12:48 PM EST
Next week will be an exciting week as I head down to San Jose for the functional verification event of the year – DVCon. This event surpasses even DAC for its relevance to the subject and in addition is heavy on practice and light on theory – just what people really need to create an immediate return on their investment – and we all know how important that is these days. Of course, DVCon is not just about verification If it weren’t for people doing design and basically getting it wrong, then verification engineers would be out of a job – so we don’t really want to encourage them to use good practices or things that will actually reduce the number of mistakes they make – OK, I hope you understand that this is said with tongue in cheek!
I have a very busy schedule with both exciting sessions and interviews I have set up with engineers, executives and yes – friends. Many of the people in this industry have been in it as long or even longer than I have and it is good to find out what is going on in their lives.
While I am not participating in the official program, I will be moderating a breakfast panel on Tuesday morning 7:00am to 8:15am in the San Carlos/San Juan room at the Doubletree. Its title - How Does Anyone Tape Out Working Chips Anymore? This panel is being organized by Breker Verification, an exhibitor at the conference.
Abstract:
Functional verification of a large, complex system-on-chip (SoC) design is a huge challenge. Simulation using standardized testbench methodologies, coupled with static and formal analysis, works quite well at the block and subsystem level. However, simulation at the full-SoC level is slow, and the existing methodologies don't link the testbench to software running on the SoC's embedded processors. Hardware-software co-verification running on an emulator or FPGA prototype checks only a specific version of software against the design and thus is not very effective at finding lurking hardware bugs.
As a result, many SoC teams tape out their chips knowing that there is a significant gap between minimal full-chip testbench simulation and emulation/prototyping. Given this reality, it's a wonder that anyone's SoC designs work. This panel considers how to increase the odds for first-silicon success by filling this gap. Panelists include both users of Breker's TrekSoC product and those trying to leverage more traditional methods. This panel is appropriate for verification engineers, verification managers, and SoC project managers who would like a better solution than they have today.
Well over 100 people attended a similar event last year and space is limited, so sign up to reserve your seat. You may register by contacting Breker at register@brekersystems.com. Hope to see you there!
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
I have a very busy schedule with both exciting sessions and interviews I have set up with engineers, executives and yes – friends. Many of the people in this industry have been in it as long or even longer than I have and it is good to find out what is going on in their lives.
While I am not participating in the official program, I will be moderating a breakfast panel on Tuesday morning 7:00am to 8:15am in the San Carlos/San Juan room at the Doubletree. Its title - How Does Anyone Tape Out Working Chips Anymore? This panel is being organized by Breker Verification, an exhibitor at the conference.
Abstract:
Functional verification of a large, complex system-on-chip (SoC) design is a huge challenge. Simulation using standardized testbench methodologies, coupled with static and formal analysis, works quite well at the block and subsystem level. However, simulation at the full-SoC level is slow, and the existing methodologies don't link the testbench to software running on the SoC's embedded processors. Hardware-software co-verification running on an emulator or FPGA prototype checks only a specific version of software against the design and thus is not very effective at finding lurking hardware bugs.
As a result, many SoC teams tape out their chips knowing that there is a significant gap between minimal full-chip testbench simulation and emulation/prototyping. Given this reality, it's a wonder that anyone's SoC designs work. This panel considers how to increase the odds for first-silicon success by filling this gap. Panelists include both users of Breker's TrekSoC product and those trying to leverage more traditional methods. This panel is appropriate for verification engineers, verification managers, and SoC project managers who would like a better solution than they have today.
Well over 100 people attended a similar event last year and space is limited, so sign up to reserve your seat. You may register by contacting Breker at register@brekersystems.com. Hope to see you there!
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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