EDA/IP weekly roundup – March 13th 2013

3/13/2013 11:33 AM EDT

This is a roundup of news or activities in the past few days that may be of interest to people.

Pulsic closed another year of double-digit revenue growth in 2012. The company completed renewal of several significant long-term customer license agreements. Along with renewal agreements, Pulsic completed delivery of a new hierarchical design flow and methodology for a leading memory company. The new flow increased automation of many tasks that were previously undertaken manually, and put automation into the hands of design managers.

Mentor Graphics has announced several new capabilities for its Flowmaster® simulation software solution for thermo-fluid systems. From concept through design, optimization, and validation, the Flowmaster products are used at every stage of development so that engineers can minimize design effort to accurately simulate fluid flow and thermal analysis of their end-products. The latest release contains several significant features for pre-processing, simulation, data management, and design collaboration.

Renesas Electronics has developed and will start supply of a multi-format video codec hardware IP product that supports low-delay processing for automotive information terminals that support High Definition Television (HDTV), mobile devices such as smartphones and tablets, and industrial equipment. This new hardware IP features a minimum processing delay of 1 ms, support for encoding functions for VP8TM video codecs, and HD (1920 × 1080) 60 fps (1080p60) performance.

Rambus has transferred a portfolio of patent assets covering display technologies to a subsidiary of Acacia Research Corporation, a patent licensing company. As part of this transaction, Rambus received an initial upfront payment and is expected to receive subsequent payments. Specific terms of the transaction are confidential.

MathWorks has announced Release 2013a of its MATLAB and Simulink product families. New in this release is the introduction of Fixed-Point Designer, which combines the functionality of Fixed-Point Toolbox and Simulink Fixed Point. Also included are capabilities within Phased Array System Toolbox and SimRF that strengthen wireless and radar communications system design. R2013a also updates 80 other products, including Polyspace embedded software verification products.

Cadence has introduced design IP (IP) and verification IP (VIP) supporting the new Mobile PCI Express® (M-PCIe™) specification. The M-PCIe IP and VIP solution enables the PCI Express architecture to operate over the MIPI® M-PHY® physical layer technology, extending the benefits of the PCIe® I/O standard to low-power mobile devices including thin laptops, tablets and smartphones.

Aldec has a new release of its mixed-language verification platform, Riviera-PRO™ 2013.02. This release includes numerous enhancements, including visual debugging tools that improve the presentation of simulation results for increased overall verification efficiency. Riviera-PRO 2013.02 includes a Plot window supporting four different plot types to enable more efficient visualization of large data sets, as well as the ability to visualize and analyze relations between any objects within a design with no additional programming required.

EMA Design Automation has announced Team Design for OrCAD facilitating schematic design in a team environment. Integrated directly inside the OrCAD Capture interface, Team Design for OrCAD allows engineers to easily view a full history of all current and previous projects. Project leads can define users and their roles, controlling design responsibilities as well as access rights to specific pages and functional blocks. Once added to a project, design team members are able to view project status, add new pages, download existing page(s) for editing, and upload any changes back into the system.

Cadence has entered into a definitive agreement to acquire Tensilica, Inc., a leader in dataplane processing IP, for approximately $380 million in cash. Tensilica had approximately $30 million of cash as of December 31, 2012. Further expanding Cadence’s IP portfolio, Tensilica provides configurable dataplane processing units that are optimized for embedded data and signal processing targeted at mobile wireless, network infrastructure, auto infotainment and home applications.

HDL Design House has announced availability of its Physical Coding Sublayer (PCS) IP core (HIP 500) which enables transmission and reception of data via an 8-Lane SerDes interface.  It is able to multiplex a synchronous data stream over 8 lanes, while guaranteeing data alignment and super-frame synchronization.

Asygn, a company specializing in Mixed-Signal IC System Design, has announced that STARC, the Japanese electronic design consortium, has selected Asygn’s Tactyle as the AMS System Level Design & Verification solution for the Japanese semiconductor industry’s next-generation STARCAD-AMS Analog/Mixed Signal reference flow.

Green Plug has released Greenscape™, a GUI-based development platform that fosters rapid prototyping and tuning of designs, targeting competitively-priced controllers that are optimally sized for each application. It contains a library of configurable hardware blocks -- such as ADCs, PWMs, DACs, comparators and other building blocks that serve power supply designers with tools to meet power supply requirements. With Greenscape, developers can make real-time changes to key thresholds, set points, startup sequences, timing, switching frequencies and more.

IAR Systems® has a new version of its development tools for STMicroelectronics’ STM8. The new version 1.40 of IAR Embedded Workbench® for STM8 adds functionality in the form of a new text editor and source browser, integration with the version control system Subversion and new license management features.

Brian Bailey – keeping you covered