EDA/IP weekly roundup – March 20th 2013

3/20/2013 11:38 AM EDT

This is a roundup of news or activities in the past few days that may be of interest to people.

Agilent Technologies is shipping their latest release of their SPICE model extraction tool, Model Builder Program, and SPICE qualification tool, Model Quality Assurance. MBP and MQA 2013 feature enhancements designed to enable device modeling engineers to deliver higher-quality models to their customers. Chief among them are an integrated data flow across Agilent’s device modeling platform and the ability to establish and enforce standard operating procedures for modeling in team environments.

Blue Pearl Software has added support of STARC (Semiconductor Technology Academic Research Center) to its Blue Pearl Software Suite, for Windows and Linux operating systems. Designers can now perform RTL analysis and ensure compliance with best practices and reuse guidelines based on the STARC rules.

Docea Power has a new release of Aceplorer 3.1 and AceThermalModeler 2.0. Aceplorer 3.1 features a new solver for coupled power and thermal transient simulations featuring 1000x performance gains over the previous versions and a communication protocol enabling the co-simulation of Aceplorer models with virtual platforms and performance analysis tools. AceThermalModeler 2.0 generates compact thermal models for System on Chips (SoCs), 3D ICs, Systems in Package (SiPs) or complete boards.

With the demands for efficiency greater than ever for North American manufacturing facilities, leading electronics distributor Newark element14 has developed a new online catalog with advanced functionality that helps to streamline the selection and purchase of products for industrial automation and control. The catalog offers multiple ways to find the right product: users can browse by product category or manufacturer or search by keyword or part number. Pricing and current availability data are instantly visible by hovering over a part number, and one click takes the user into a detailed information page with access to 24/5 live technical support and a shopping cart.

Imec has launched its integrated silicon photonics platform through a cost-sharing Multi-Project Wafer (MPW) service via ePIXfab*. The platform enables cost-effective R&D of silicon photonic ICs for high-performance optical transceivers (25Gb/s and beyond) and optical sensing and life science applications. The offered integrated components include low-loss waveguides, efficient grating couplers, high-speed silicon electro-optic modulators and high-speed germanium waveguide photo-detectors. The first run opens for registration with tape-in on 9th of Oct 2013 and first devices will be out in May 2014. Support, registration and design kit access will be organized by Europractice IC service, in collaboration with world-wide MPW partners.

Mentor Graphics has announced the Nucleus® SmartFit product, a binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs. The Nucleus SmartFit product also includes Sourcery™ CodeBench development tools and provides developers with broad connectivity and power consumption options for developing products based on 32-bit microcontrollers (MCUs).

ARM Holdings has announced that Chief Executive Officer Warren East has decided to retire from the company, effective 1 July 2013, after nearly twelve years as CEO and nineteen outstanding years at the company.   Simon Segars, currently President of ARM, will become the company's new CEO.

CriticalBlue has announced that Kathryn Kranen, President and CEO of Jasper Design Automation, has joined its Board of Directors. Kranen brings more than 20 years EDA industry experience and a proven business track record to the CriticalBlue Board. Kranen has been responsible for leading Jasper’s team in successfully bringing the company’s pioneering technology to the design verification market. She is chairman of the EDA Consortium board of directors and is serving her eighth elected term on the EDAC board.

Oasys Design Systems now has physically-aware register retiming capability for improved quality of results (QoR) available in the Oasys RealTime synthesis engine. Register retiming is a technique of moving the structural location of registers in a digital circuit to improve its performance, area, and power characteristics in such a way that preserves its functional behavior at its inputs and outputs. The RealTime synthesis engine automatically moves registers through combinational logic to balance and optimize the delay across each stage of a pipeline.

STMicroelectronics and CMP announced that ST’s THELMA MEMS manufacturing process, the process ST uses for its accelerometers and gyroscopes, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as a prototyping and foundry service to encourage new developments in motion-sensing applications for consumer, automotive, industrial and healthcare markets.

Global Unichip has a new family of silicon proven digital-to-analog converter (DAC) and analog-to-digital converters (ADC) IP targeting TSMC's 28nmHPM process technology. The new family includes a SAR(Successive Approximation Register) ADC , R2R (R-2R resistor ladder network) DAC and a Current DAC macros, plus a new thermal sensor macro.

Accellera Systems Initiative has completed the SystemC® Analog /Mixed-Signal (AMS) 2.0 extensions. SystemC AMS 2.0 is an industry-driven mixed-signal standard for electronic system-level design. The SystemC AMS 2.0 language reference manual (LRM) is available for download under SystemC open-source license at www.accellera.org. The update of the AMS extensions contains additional features to model dynamic and reactive mixed-signal behavior at high levels of abstraction. New semantics and language constructs complement the standard to address modeling accuracy, fidelity and speed for efficient mixed-signal system-level design. A main feature of the updated standard is the introduction of dynamic features for the Timed Data Flow (TDF) model of computation.