Well, I'm still trying to wrap my brain around this one… I just heard from my chum Tobias Strauch, who is the founder of EDAptix
in Munich Germany.
It seems that for the past few years Tobias has been working on a rather cool technology called System Hyper Pipelining
in which he uses registers to multiply the functionality of IP cores.
In his own words, the example Tobias gives is as follows: "You can usually get only one ARM-compatible core (e.g. Amber from OpenCores) on a Spartan-6 LX9 FPGA running at 60MHz. With System Hyper Pipelining I can multiply this functionality and run 16 cores with an equivalent system performance of 250MHz!"
If you are interested in learning more about this technology, Tobias invites you to bounce over to www.cloudx.cc
and take a look around. In particular, he says you should check out the technology video.
Tobias also has a demo that runs on his low-cost FPGA Arduino board, an image of which I just snagged from the left-hand side of his projects page at www.cloudx.cc/projects.html
As part of a spirited email conversation, Tobias added the following: Maybe I should clarify the 250 MHz a little bit. The following rules exist in the demo:
- You have to run 5 ARMs.
- Each processor runs at a maximum speed of 50MHz (*5 = 250MHz),
- You can distribute the 250MHz among up to 16 ARMs
- Any intermediate scenario is possible (3 @ 50MHz + 5 @ 20MHz = 250MHz).
Tobias is really excited about this – he feels that this System Hyper Pipelining technology is revolutionary, especially when you compare it with the fact that a single ARM only runs at 60MHz.
The problem, he says, is that this technology is so cool that it is very hard to explain and/or sell to people, which is why (a) he created his demo and (b) he asked me to spread the word (grin).
Please do bounce over to www.cloudx.cc
and take a look around, and then comment below to tell us what you think.
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