Programmable Logic DesignLine Blog
My brain hurts!
Clive Maxfield
2/4/2013 11:44 AM EST
I think I may have "over-indulged" yesterday evening whilst watching the Super Bowl – I was certainly "relaxed and refreshed and feeling no pain," as it were.
The problem is that things all seem to be a little "fluffy" around the edges this morning – I'm finding it a tad difficult to get my brain to go into gear – it's like trying to fire-up a car that doesn’t want to start – you keep on turning the key and the engine sort of splutters into life – and then it judders to a graunching halt again.
This might explain why I'm having so much difficulty wrapping my brain around a question that just came winging its way across the Internet to me. But first, let's set the scene. In Chapter 6 of my book Bebop to the Boolean Boogie: An Unconventional Guide to Electronics (still the only electronics book in the world to include a Seafood Gumbo recipe) we consider how to construct primitive logic gates using CMOS technology (PMOS and NMOS transistors connected together in a complementary manner).
We start off with a simple inverter function in the form of a NOT (or INV) gate as shown below. If input 'a' is presented with a logic 0 (for example, if we used a wire to connect it to the VSS line), then NMOS transistor Tr2 will be turned Off, PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VDD (logic 1) via Tr1.
Similarly, if input 'a' is presented with a logic 1 (for example, if we used a wire to connect it to the VDD line), then PMOS transistor Tr1 will be turned Off, NMOS transistor Tr2 will be turned On, and output 'y' will be connected to VSS (logic 0) via Tr2.
I then go on to explain that a non-inverting BUF (buffer) gate is more complex than a NOT gate. This is due to the fact that a BUF gate is essentially constructed from two NOT gates connected in series as shown below:
So far, so good. But now we move to consider the email I just received, which reads as follows:
Well, you have to admit that he writes a very nice message. So here I am sitting looking at his suggested circuit. I can absolutely see where he's coming from. At the same time, I know this won’t work, because I know you can't connect the PMOS and NMOS transistors together in this way. The problem is that – as I mentioned above – my poor old brain is limping along at a fraction of its usual speed, and I find myself unable to articulate why this won’t work.
What say you? How can we put this into words that he (and I) will understand?
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The problem is that things all seem to be a little "fluffy" around the edges this morning – I'm finding it a tad difficult to get my brain to go into gear – it's like trying to fire-up a car that doesn’t want to start – you keep on turning the key and the engine sort of splutters into life – and then it judders to a graunching halt again.
This might explain why I'm having so much difficulty wrapping my brain around a question that just came winging its way across the Internet to me. But first, let's set the scene. In Chapter 6 of my book Bebop to the Boolean Boogie: An Unconventional Guide to Electronics (still the only electronics book in the world to include a Seafood Gumbo recipe) we consider how to construct primitive logic gates using CMOS technology (PMOS and NMOS transistors connected together in a complementary manner).
We start off with a simple inverter function in the form of a NOT (or INV) gate as shown below. If input 'a' is presented with a logic 0 (for example, if we used a wire to connect it to the VSS line), then NMOS transistor Tr2 will be turned Off, PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VDD (logic 1) via Tr1.
Similarly, if input 'a' is presented with a logic 1 (for example, if we used a wire to connect it to the VDD line), then PMOS transistor Tr1 will be turned Off, NMOS transistor Tr2 will be turned On, and output 'y' will be connected to VSS (logic 0) via Tr2.
I then go on to explain that a non-inverting BUF (buffer) gate is more complex than a NOT gate. This is due to the fact that a BUF gate is essentially constructed from two NOT gates connected in series as shown below:
So far, so good. But now we move to consider the email I just received, which reads as follows:
Respected sir,
I read your book "Bebop to the Boolean Boogie" and found it really amazing. The matter has been presented in a very friendly tone and easy to understand style. It really helped me to thoroughly understand the concepts.
But, I would like to bring into your consideration a small mistake from the book. In the chapter 'Using Transistors to Build Primitive Logic Functions' it is written that for building a CMOS Buffer, four transistors are required. But i think, interchanging the positions of the NMOS and PMOS transistors in the NOT circuit (given in the book) can give a Buffer and this technique uses only two transistors. Please find an image file attached with this email with a circuit diagram.
Am I right? Or is there a flaw in the above technique? Except for this, I found the book very good and I will surely recommend it to my peers.
Thank you sir for your consideration.
Well, you have to admit that he writes a very nice message. So here I am sitting looking at his suggested circuit. I can absolutely see where he's coming from. At the same time, I know this won’t work, because I know you can't connect the PMOS and NMOS transistors together in this way. The problem is that – as I mentioned above – my poor old brain is limping along at a fraction of its usual speed, and I find myself unable to articulate why this won’t work.
What say you? How can we put this into words that he (and I) will understand?
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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elizabethsimon
2/4/2013 12:48 PM EST
The problem with the circuit that he proposed is that the PMOS FET requires a negative voltage on the gate with respect to the source and drain in order to turn on. So in the proposed configuration the voltage at point a would have to be below Vss to turn the PMOS FET on. Similarly, the NMOS FET requires a positive voltage to turn on which would be higher than Vdd.
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dneves
2/5/2013 12:25 PM EST
I would expect it to kind of work, but it should act more like a "des-amplifier". As I see it, when A is high the upper NMOS will look like a diode connected MOS, thus the output voltage Y will never be able to reach Vdd. The same for the lower PMOS device, when A is low, it is connected like a diode and Y will never reach VSS...
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betajet
2/5/2013 1:35 PM EST
Assuming that input "a" can go as high as Vdd, the upper NFET can only pull the output as high as Vdd-Vth, where Vth is the threshold voltage of the NFET. The NFET is in saturation mode (see http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation). Similarly, if "a" can only go as low as Vss the PFET can only pull the output down to Vss+Vth. dneves' description of it as a "des-amplifier" is a good way to put it.
High-side NFETs are often used in power electronics since NFETs are so much more efficient than PFETs, but they have boost circuits to drive the NFET's gate many volts higher than its drain and source.
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elektryk321
2/6/2013 6:58 AM EST
Proposed circuit seems to be electrical correct, but real integrated circuts are manufactured on "typical" silicon substrate where doped areas has parralel stripes and always NMOS transistor is "higher" and PMOS transistor is "lower" on the picture. Also power lines are distributed to make short connections between Vcc to PMOS and GND to NMOS. Any odds to this rules will make integrated circuit bigger and more expensive.
Layout of not-gate, looks like http://www-scf.usc.edu/~ee577/graphics/magic_tut/magic29.jpg
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dneves
2/6/2013 7:03 AM EST
To put it in simpler terms for those (like myself) that are not analog experts. If one assumes a MOS to behave like an ideal switch all the times, the unconventional buffer design should have worked. The problem resides that one can only approximate the MOS transistors as ideal switches under certain (very strict) conditions. By swapping around the transistors on a standard inverter, the conditions that lead to the MOS behaving like a switch (i.e. in the triode region) are no longer met for both transistors, and those devices will acquire a more complex behavior instead (i.e. saturation region instead). That is why the circuit ends up not working as expected...
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Max the Magnificent
2/8/2013 1:42 PM EST
This is a great answer -- thanks for sharing
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Ed Baker
2/6/2013 7:52 AM EST
When a is at Vdd/2 won't both transistors switch on and let the smoke out? They are analog(ue) after all. :)
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Max the Magnificent
2/8/2013 1:44 PM EST
Yes -- this is a problem whenever the input is switching from 0 to 1 or vice versa, because there is a time in the middle of the switch when both transistors are at least partially active providing a short from Vdd to Vss -- fortunately this occurs for a very short time indeed
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bcarso
2/6/2013 4:33 PM EST
The principal problem is that each part becomes a source follower, which has less than unity gain. Even if the threshold voltages are adjusted in the process to allow for significant output voltage swings, there will always be input to output voltage swing lost. So use with other gates will always be severely constrained.
Brad
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Davidcj
2/7/2013 2:06 PM EST
Basic misunderstanding is that FETs are polarity dependent devices. An N channel FET requires the drain to be more positive than the source, and a P channel requires the opposite. Reversing them, as suggested, reverses the polarities on the FETs and will not work.
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whatshisface
2/7/2013 7:09 PM EST
Most of the comments above are correct. We also need to remember that the FET source/drain terminals are electrically defined. They can change position with bias and routinely do in techniques such as pass transistor circuits, transmission gates and the like.
In this circuit, just looking at the PMOS, the drain is defined as the top terminal (as long as the output is "high"). Thus, as already pointed out, it is impossible to achieve a -Vgs as required by the PMOS unless Vg is taken to a negative voltage. Ergo, it will not work as you can never get the PMOS "on". The argument for the NMOS is a little different. It can be switched "on" but when the output reaches Vdd-Vth, it turns "off" again.
I suggest that you advise him/her to try it using PSpice or equivalent. It would take 10 minutes or so for it to become completely clear.
In reply to Ed Baker, that indeed happens during switching, and is the source of the so-called "dynamic power" (aFCV^2) that is causing so much trouble at the moment. No smoke, but potential fire as switching power densities get ridiculous :-)
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David Ashton
2/7/2013 7:37 PM EST
As I recall FETS act not so much as switches but as constant current sources? So if both are on with A at Vdd/2 you'll get a defined current flow through both of them, not a huge (ie smoke-liberating) current. This is used in some applications that use CMOS as linear amps, they're not great but they work.
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David Ashton
2/7/2013 7:40 PM EST
Fairchild actually put out an app note for using CMOS like this:
http://www.fairchildsemi.com/an/AN/AN-88.pdf
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DrQuine
2/7/2013 10:31 PM EST
Disproving such a proposal is best accomplished by trying it out. Sometimes the results are unexpected and you may learn something. What actually happens when the proposed circuit is constructed? Do the behavior and behavior match the predictions above? With observations in hand, will some adjustments make a difference? [Unfortunately, I don't have the resources to try it out myself.)
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Max the Magnificent
2/8/2013 1:47 PM EST
I agree -- what we need now is someone with the required FETs and a test bench -- if all else fails I'll pick some up from Mack Electronics when i visit them on Monday as I just mentioned in the following blog eetimes.com/electronics-blogs/other/4406626/What-light-through-yonder-window-breaks-?Ecosystem=programmable-logic
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seaEE
2/7/2013 11:20 PM EST
I agree with DrQuine, try it out. Next week we can see if the column is titled Max's Hot FETs.
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ecrahuljain
2/8/2013 2:06 AM EST
the problem lies here in the design itself as ....
when considering the n-mos .... when 'a' terminal is logic 'high' ie equal to 1 then the n-mos transistor is in cutoff mode since the Vgs here would be 1-1=0 thus would be less than Vth ie threshold and thus would not conduct hence the above design is faulty....
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eugen.saffert
2/11/2013 4:27 AM EST
Hi Max,
there is a typo in your artikle just above the NOT gate truth table where it says:
"PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VSS (logic 1) via Tr1."
Tr1 of course connects the output to VDD not VSS.
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Max the Magnificent
2/11/2013 6:14 PM EST
Arrgghhh!!! Good catch -- I just went back and fixed it -- thanks for the "heads up" -- Max
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bcarso
2/13/2013 3:27 PM EST
If the FETs are depletion mode devices (most JFETs are, some DMOS are) then think of the circuit as a complementary source follower, with slightly less than unity voltage gain for mid-rail signals. Such circuits are not that unusual as analog domain buffers.
But as I stated above, for logic we have a problem even with such devices, as the voltage gain is always less than unity. Inverters have voltage gain. Non-inverters do not unless they have embedded within them inverters :)
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