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DKC

8/3/2010 2:28 AM EDT

"The SystemC classes include the basic extensions necessary for accurate ...

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eewiz

7/26/2010 2:56 PM EDT

I think the main problem with HLS is that, the implementation efficiency hasn't ...

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Dispelling the myths of High-Level Synthesis

Brett Cline

7/15/2010 7:57 AM EDT

High-level synthesis (HLS) has been a hot topic for about the last 10 years, characterized as Electronic System Level (ESL) synthesis, algorithmic synthesis, and behavioral synthesis, and C synthesis by some. I just call it “simply, a better way to design hardware.”

Regardless of which bucket HLS goes in, there has been a significant shift in the market over the last year with increased adoption in the United States and all over the world. Still, a lot of misinformation exists about the state of the technology.

In a recent online exchange, I found myself dispelling some of these myths and that led me to consider why this happens. Of course, there is good old fashioned FUD (fear, uncertainty, and doubt) spread by competitors, but this was more than that. It was a genuine misunderstanding about what is going on in with real design teams using HLS in production flows.

In the last five years, companies have used SystemC and high-level synthesis to deliver a number of products. These products range from HDTVs, digital still cameras, video cameras to commercial multi-function printers, hearing aids, USB and SSD controllers, HDMI interfaces, DVD players and wireless and broadband devices.

And, that is just what has been done! Imagine what is going on today with the hundreds of designs that are being done right now and set for release in the coming months and years. Still, with all of this success, there’s disagreement about how to get started.

One of the biggest areas of controversy about HLS tools is not about the tool at all, but the language. Last time I counted, there were more than 10 HLS tools on the market with input languages including ANSI-C, C++, SystemC and M. I’m sure there are others. Why, then, does the controversy exist and what are the major issues?

Choosing a language for high-level design may be the most important choice you will make. As a result, plenty of thought and care should go into making the decision. Of course, standards are important and, frankly, each language listed above is a standard in one way or another, so that doesn’t provide much clarification.

Many people also consider “legacy” in terms of “what format is my code in today?” This also is problematic because the code and language may not have been developed with hardware design in mind.

I think the decision should answer the two questions above but, fundamentally, it comes down to: “What are you trying to accomplish now and in five years?”

The language decision is about far more than just high-level synthesis. It’s about designing with platform creation and virtual system prototyping tools, high-level verification tools, debug and analysis, intellectual property, high-level synthesis and many, many more pieces of a complete ecosystem.

Perhaps you’ve heard me explain or read articles by other members of the Forte team about why we think that SystemC is the right “language” for high-level design and HLS. Based on my recent online experience, perhaps not.

As an aside, SystemC (IEEE 1666) is not technically a language at all. SystemC is a C++ class library that extends C++ in a standardized way. The SystemC classes include the basic extensions necessary for accurate hardware modeling, including bit accuracy, clock accuracy, concurrency and hierarchy. In addition, the SystemC classes implement a simulator that can be used to execute the design model with only a standard GNU compiler.

It’s time that design teams reevaluate their methodologies, investigate new tools and flows, and generally get an update about what is going on in the EDA industry. Many of you will look beyond RTL this year, some for the first time. As you look around and consider the high-level synthesis market, check out Forte. We’ve been synthesizing production ASICs, SoCs, and FPGAs with SystemC since 2002.

About the author:


Brett Cline is vice president of marketing and sales at Forte Design Systems (San Jose, Calif.).


Before joining Forte in 1999, Cline was director of marketing at Summit Design, where he managed both the verification product line and marketing communications. Cline has also held positions in development, applications and technical marketing at Cadence Design Systems and General Electric.


He holds a Bachelor of Science degree in Electrical Engineering from Northeastern University in Boston and serves on the Board of Directors of Provis Corporation in Minneapolis.





Moca

7/15/2010 9:58 AM EDT

Why SystemC is technically not a language has to do with whether it is the "right" language or not?

You did not explain at all why it is not the right language.

My experience is, it is faster to learn systemC than trying to struggle writing model in C which has no concurrent capability.

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Matt Thayer

7/21/2010 8:50 PM EDT

What?

Did this actually dispel any myths?

All I saw here was a brief introduction, followed by "It's important to choose the right language. I like SystemC. Check out my company"

Did I miss the bulk of the article, or is this just an ad piece for HLS awareness and services?

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kiku_#1

7/23/2010 12:32 AM EDT

I agree with Matt Thayer. The article doesn't dispel any myths. Let alone dispelling, it does not even mention any of them.

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eewiz

7/26/2010 2:56 PM EDT

I think the main problem with HLS is that, the implementation efficiency hasn't reached that of the RTL level HDL Synthesis. Therefore most engineers, think of SystemC/HLS as immature tech.
Ofcourse, if you carefully follow, the "synthesisable subset" and "templates" specified by the Forte/HLS tool your results are very close to that of HDL/RTL synthesis. But then you can do the same thing in available HDLs AND much superior EDA tools available for synthesis.

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DKC

8/3/2010 2:28 AM EDT

"The SystemC classes include the basic extensions necessary for accurate hardware modeling"

- not really. It might be sufficiently accurate to test your software (on a digital system), but it knows nothing about analog stuff (like power management), or RF.

The methodology is rooted in a 1990's cycle-based simulation approach which relies too much on shared memory to be MT-safe (so it doesn't run parallel).

If you want something that is actually an extension of C++ for ESL/HLS and hardware modeling have a look at this -

http://parallel.cc

- and you can use it for writing parallel code (you don't see programmers rushing to use SystemC for anything).

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