Semi Conscious
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Pablito
Let's be clear there is SOI for today which is partially depleted, and SOI for ...
daleste
SOI is more expensive since it takes a special starting material that is not yet ...
SOI's long and winding road: Are we there yet?
Dylan McGrath
8/4/2010 9:38 PM EDT
It's been a long, meandering road for silicon-on-insulator (SOI) technology. Revenue from SOI wafers grew nicely in the early 2000s after it was adopted by a handful of high-profile chip makers including IBM and AMD. Now, after a lull, some—including the market-leading supplier of SOI wafers—say the technology is ready for a second wave of adoption.
"SOI grew very nicely once IBM and AMD adopted it," said Risto Puhakka, president of market research firm VLSI Research Inc. "That drove the business very nicely for three or four years. But, then like everyone else, they saw the downturn and that kind of limited things for SOI."
Soitec SA, founded more than 10 years ago to commercialize SOI wafers, said last month it expects to cross into profitability sometime during the next three months for the first time since the first half of its fiscal year 2007.
Soitec posted revenue for its fiscal first quarter of $68.6 million euros, an increase of nearly 57 percent compared to the year-ago period. With challenges aplenty facing continued scaling of bulk CMOS technology, Soitec executives believe the industry is poised for wider SOI adoption.
At the Semicon West tradeshow last month, Soitec announced an ultra-thin buried oxide (UTBOX) extension to its ultra-thin SOI platform, a development the company hailed as a key milestone to spur wider adoption of SOI wafers. According to the company, designers working on fully depleted planar body transistors—prescribed by the International Technology Roadmap for Semiconductors (ITRS) for the 22-nm node and beyond—using UTBOX wafers can enhance their existing design flows and techniques rather than adopting entire new methodologies and toolsets.
According to Soitec, UTBOX wafers promise better electrostatic transistor characteristics, a larger choice of design-level techniques for power and performance optimizations and simple co-integration of legacy bulk CMOS structures.
Paul Boudre, Soitec's chief operating officer, described the required design process enhancements as an "evolution" as opposed to a "revolution." This is a key point, because historically chip companies tend to favor new technology that causes less disruption to existing methodologies to enable continued scaling.
The 2009 ITRS calls for chip makers to be using ultra-thin body fully deleted SOI MOSFETs and multi-gate MOSFETs such as FinFETs in production in 2013 or later. According to Boudre, both benefit from SOI. He predicts that while the larger chip companies like Intel Corp. may implement FinFETs or tri-gate transistors in future devices, the bulk of chip makers will turn to planar fully depleted SOI MOSFETs. Or companies might go with FinFETs for high-performance devices like microprocessors and choose the planar path for other devices, he said.
"We believe this is the only platform that will be planar down to the 11-nanometer node," Boudre said. "It will sustain Moore's Law."
"SOI grew very nicely once IBM and AMD adopted it," said Risto Puhakka, president of market research firm VLSI Research Inc. "That drove the business very nicely for three or four years. But, then like everyone else, they saw the downturn and that kind of limited things for SOI."
Soitec SA, founded more than 10 years ago to commercialize SOI wafers, said last month it expects to cross into profitability sometime during the next three months for the first time since the first half of its fiscal year 2007.
Soitec posted revenue for its fiscal first quarter of $68.6 million euros, an increase of nearly 57 percent compared to the year-ago period. With challenges aplenty facing continued scaling of bulk CMOS technology, Soitec executives believe the industry is poised for wider SOI adoption.
At the Semicon West tradeshow last month, Soitec announced an ultra-thin buried oxide (UTBOX) extension to its ultra-thin SOI platform, a development the company hailed as a key milestone to spur wider adoption of SOI wafers. According to the company, designers working on fully depleted planar body transistors—prescribed by the International Technology Roadmap for Semiconductors (ITRS) for the 22-nm node and beyond—using UTBOX wafers can enhance their existing design flows and techniques rather than adopting entire new methodologies and toolsets.
According to Soitec, UTBOX wafers promise better electrostatic transistor characteristics, a larger choice of design-level techniques for power and performance optimizations and simple co-integration of legacy bulk CMOS structures.
Paul Boudre, Soitec's chief operating officer, described the required design process enhancements as an "evolution" as opposed to a "revolution." This is a key point, because historically chip companies tend to favor new technology that causes less disruption to existing methodologies to enable continued scaling.
The 2009 ITRS calls for chip makers to be using ultra-thin body fully deleted SOI MOSFETs and multi-gate MOSFETs such as FinFETs in production in 2013 or later. According to Boudre, both benefit from SOI. He predicts that while the larger chip companies like Intel Corp. may implement FinFETs or tri-gate transistors in future devices, the bulk of chip makers will turn to planar fully depleted SOI MOSFETs. Or companies might go with FinFETs for high-performance devices like microprocessors and choose the planar path for other devices, he said.
"We believe this is the only platform that will be planar down to the 11-nanometer node," Boudre said. "It will sustain Moore's Law."
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daleste
8/6/2010 3:25 PM EDT
SOI is more expensive since it takes a special starting material that is not yet in very high volume and there tends to be more processing steps. The big avantage is the reduced leakage current (power consumption) and it eliminates the SCR latch up inherent in CMOS so the layout can be more dense with less guard rings. It is great for dense high speed digital logic. Of course, high power and analog functions can't go there.
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Pablito
8/18/2010 5:25 PM EDT
Let's be clear there is SOI for today which is partially depleted, and SOI for tomorrow: fully depleted, Finfet or other novel structure.
Partially depleted SOI is dying, I believe 32nm may be its last hurrah. Every generation, drain cap scales reducing the advantage. More important, it really limits how effectively one can put SiGe strain, a strong performance booster, this one really used by Intel.
Can't help a comment on the cost, yes AMD is using it in volume production, but when is last time they made money, and how much money is Intel making in comparison?
SOI for tomorrow is a different animal. In this case, tomorrow is still a few years away.
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