New techniques for PDN modeling promise more accurate power noise predictions
9/3/2010 5:13 AM EDT
“The bad news is that power distribution noise requirements will be getting more difficult to meet. And the really bad news is that the actual on-die power noise you currently have is probably much larger than you think.” This is the message from Larry Smith, signal and power integrity architect at Altera Corp.
Over the last few years, Smith and his team, including Shishuang Sun, have been investigating on-die power rail noise to develop accurate models useful in system simulation for cost-performance optimized FPGA designs. As part of this effort, his team designed and fabricated a special test chip using 65-nm technology with over 100,000 toggle flip flops. The chip was assembled in a custom BGA instrumented to directly measure the on-die voltage rails and the printed circuit board (PCB) voltage rails.
Experimental test chip and package to directly measure on-die and on-board power noise.
It’s the on-die power rail noise that will directly affect jitter and timing margins. The rail voltage level directly affects propagation delay; lower voltage results in longer propagation delay. But, PDN noise specs usually refer to the noise on the circuit boards, when in reality it is the noise on the die that determines the impact on jitter.
Normally, directly measuring the voltage on-die is impossible to do, which is why the Altera team built a specially instrumented chip and package. The alternative is to use accurate models of the switching currents, the on-die capacitance and the package and its associated chip and board attach elements to simulate the on-die noise. This is the ultimate goal of Smiths’ effort.
As an example of the difference between on-die rail noise and circuit board rail noise, the worst case switching current pattern through the test chip produced 577 mV of peak to peak noise on the chip’s rails, but only 48 mV of noise on the circuit board rail. This is more than a factor of 10 difference.
Measured rail voltage noise when imposing a worst case current pattern.