New techniques for PDN modeling promise more accurate power noise predictions
9/3/2010 5:13 AM EDT
“The package lead inductance filters the on-die noise from the circuit board noise,” Smith says. “Even if the on-board PDN noise is low, as might be seen on a well decoupled board, this is no guarantee the on-die noise will be low. It could be more than 10x higher.”
The way to reduce the on-die PDN noise is by identifying the root cause and investigating the relative cost-performance benefits of different design approaches, Smith advocates.
Smith is the first to acknowledge that a full 3D electromagnetic simulation of the chip rail, package power network and board interface, coupled to a transistor level simulation of the chip might predict performance, but he says, the results might not add to your insight into the nature of the limitations or point to what direction to head to improve performance.
His team set about to build a simple, scalable model for the gates’ switching currents and identify the key design features in the die, package and board that affects the on-die PDN noise. Part of the motivation for a test chip was to validate this simplified approach.
The results of their study have been reported at the Custom Integrated Circuits Conference in 2009 and at DesignCon 2010.
Their model describes switching currents as impulses synchronous with the clock’s leading edge. Each impulse has a fast rise, typically on the order of 400 psec for the test chip used, and a rapid exponential drop. The integrated charge in one cycle is related to the number of gates switching and the amount of interconnect capacitance they drive.
Smith developed a simple, parameterized impulse function to describe this transient current. The average current increases with clock frequency, as more impulses of the same amount of charge flow through the die per unit time. By simulating different clock driven current patterns through a model of the impedance of the entire PDN, he could evaluate the PDN noise at different locations and compare it to the test chip measurements.
This model, for the specific features of the test chip and BGA package, gave transient noise values that matched measured values to a few percent accuracy.
“It’s the parallel resonance peaks in the frequency domain response of the PDN impedance that generates all the power rail noise problems,” Smith says. And these are often generated at the boundaries of elements, between the VRM and the circuit board capacitors and between the package inductance and the on-die capacitance.
This means it is not possible to optimize a part of the system and hope to manage the parallel resonances. “To really address the PDN issue, the entire system must be considered including the chip, package and PCB. Parallel resonances are a property of the system, not of any one single element.”
In a well decoupled circuit board, the dominant parallel resonance is between the package inductance and the on-die capacitance. When frequency components of the transient currents overlap this peak impedance, voltage noise results.
The transient voltage rail noise from a single impulse tells a lot of the story about the role of the on-die capacitance and the package inductance, Smith says.