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iniewski
Don: a quick comment on air gaps. Since air has the lowest possible dielectric ...
IEDM: A perspective from afar
Don Scansen
12/10/2010 12:31 AM EST
Celebrating innovation
Back to the flash session, there is obviously a lot of work going on there. Some of it proposes material changes like TaN metal gates (North Carolina State University) and high-K dielectrics in the floating gate format. Besides this and the Intel-Micron paper on 25-nm NAND and Samsung's 27-nm offering, there are also four papers on charge trapping flash. It certainly appears that charge storage non-volatile memory continues its march. The splash made by the Techinsights product discovery should not cause a panic.
Innovation—particularly at IBM was celebrated at IEDM this year with several awards to IBM researchers. Consider the three citations in relation to the recent discussions about technology development internally versus the outsourced model of chip production.
The 2010 IEEE Cledo Brunetti Award was given to Ghavam G. Shahidi, IBM T.J. Watson Research Center, "For contributions to and leadership in the development of silicon-on-insulator CMOS technology."
The 2010 IEEE Andrew S. Grove Award was presented to Bijan Davari, IBM T.J Watson Research Center, "For contributions to high performance deep-submicron CMOS technology."
The 2010 IEEE Frederik Philips Award went to John E. Kelly III, IBM, "For leadership in the development and commercialization of silicon technology and for forging industry-university partnerships for semiconductor research and development."
And if you are a foundry customer, you take comfort knowing TSMC is keeping pace in advanced technologies. A development team presented a paper on advanced FinFET structures. "High Performance 22nm FinFET CMOS Devices with Advanced High-K / Metal Gate Scheme" was authored by C.C. Wu and a long list of contributors.
Finally, as we see possibilities emerging for 22-nm logic and nodes beyond, silicon replacements and non-planar structures each offer a path. As if to make the point that they are aggressive in both those sandboxes, Intel presented, "Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications" by M. Radosavljevic and others.
I'm already looking forward to next year in DC. Hopefully, I will get a bit closer to the action.
Back to the flash session, there is obviously a lot of work going on there. Some of it proposes material changes like TaN metal gates (North Carolina State University) and high-K dielectrics in the floating gate format. Besides this and the Intel-Micron paper on 25-nm NAND and Samsung's 27-nm offering, there are also four papers on charge trapping flash. It certainly appears that charge storage non-volatile memory continues its march. The splash made by the Techinsights product discovery should not cause a panic.
Innovation—particularly at IBM was celebrated at IEDM this year with several awards to IBM researchers. Consider the three citations in relation to the recent discussions about technology development internally versus the outsourced model of chip production.
The 2010 IEEE Cledo Brunetti Award was given to Ghavam G. Shahidi, IBM T.J. Watson Research Center, "For contributions to and leadership in the development of silicon-on-insulator CMOS technology."
The 2010 IEEE Andrew S. Grove Award was presented to Bijan Davari, IBM T.J Watson Research Center, "For contributions to high performance deep-submicron CMOS technology."
The 2010 IEEE Frederik Philips Award went to John E. Kelly III, IBM, "For leadership in the development and commercialization of silicon technology and for forging industry-university partnerships for semiconductor research and development."
And if you are a foundry customer, you take comfort knowing TSMC is keeping pace in advanced technologies. A development team presented a paper on advanced FinFET structures. "High Performance 22nm FinFET CMOS Devices with Advanced High-K / Metal Gate Scheme" was authored by C.C. Wu and a long list of contributors.
Finally, as we see possibilities emerging for 22-nm logic and nodes beyond, silicon replacements and non-planar structures each offer a path. As if to make the point that they are aggressive in both those sandboxes, Intel presented, "Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications" by M. Radosavljevic and others.
I'm already looking forward to next year in DC. Hopefully, I will get a bit closer to the action.
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iniewski
12/10/2010 11:21 AM EST
Don: a quick comment on air gaps. Since air has the lowest possible dielectric constant its use in silicon has been contemplated for several years to reduce parasitic capacitance. I believe the concept was first used by STM by introducing Silicon on Nothing (SON) technology for MOSFET. Others followed, there are a few patents on use of air gaps. I guess the challenge is on how to make them reliably and prevent anything (moisture?) getting inside them. But sealing silicon die seems easy to so where is the challenge? Anyone? Kris
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