Book Review: FPGA-Based Prototyping Methodology Manual

Synopsys, in cooperation with Xilinx, ARM, LSI and nVidia, has just released a new book on the subject of FPGA-Based prototyping – one of my favorite subjects (Click Here to visit the appropriate webpage on the Synopsys site).

I managed to get a copy of the FPGA-Based Prototyping Methodology Manual (FPMM) only a couple of days ago, so I haven’t had a lot of time to read and write this review. It is one of the bad aspects of being an author in that it becomes impossible, at least for me, to read anything without wanting to mark it up and edit it. Oh well, back to the reading...

Written by Doug Amos and Rene Richter of Synopsys and Austin Lesea of Xilinx, the FPMM aims to provide a set of best practices for design-for-prototyping, but does it deliver?

The book starts with a wonderful foreword from Helena Krupnova of STMicroelectronics. She says that there are three laws associated with prototyping:

1. SoCs are larger than FPGAs
2. SoCs are faster than FPGAs
3. SoC designs are FPGA-hostile

She goes on to say that the book successfully addresses all three of these and makes a point about the ‘make’ versus ‘buy’ decision associated with build your own prototypes. The book is composed of 15 chapters (and two appendixes) that are roughly organized in terms of the processes that a novice user would need to gain in order to successfully build a prototype. People with more experience may find it possible to skip around various chapters so that they only have to read the sections in which they want to expand their knowledge.

Chapter 1 talks about the growing importance of software and the need to be able to start software development sooner. It then talks about the types of prototypes that can allow that earlier start as well as other usage models that a prototype enables along with the specific requirements to meets each of those needs. It is a well written chapter and I hope they make this chapter available for everyone so that people not yet familiar with prototyping may get to learn the types of use models and benefits that prototypes can provide. Right here would be a good place for them to make it available!

Chapter 2 dives a little further into the benefits and costs associated with an FPGA-based prototype and tries to convince you that this is the right way for you to go. I love one quote “We can generalize that, at each layer of the [SW] stack, a software developer only needs a model with enough accuracy to fool his [sic] own code into thinking it is running in the target SoC”. The success stories are told from various companies who have successfully deployed FPGA-based prototyping. The chapter then moves to the general problems associated with mapping SoCs into FPGAs and to ensure that a potential user understands that simulators and prototypes are different.

Chapter 3 takes a look at what was then (just last week) the state of the art in terms of FPGA hardware and software. More importantly, it outlines the flow that is to be used during the design and verification flow. It provides a cursory look at how certain kinds of structures are mapped into FPGAs and the mechanisms available to increase visibility and perform debug. This is a dry chapter, but it is all necessary information for those coming at this for the first time.

Chapter 4 is by far the most important chapter so far in that it outlines the steps necessary for a successful FPGA prototyping venture. It talks about sizing both from the FPGA and the SoC perspective. Given that everything so far has talked about the Xilinx Virtex 6 family, it was a bit of a surprise to then see Table 8, which says how many Virtex 5s are required for some common IP blocks. I like the fact that the chapter adds a little bit of realism, telling users exactly what to expect in terms of getting the first iteration of a prototype up and running.

Chapter 5 deals with making your own prototyping board. Since Synopsys has a lot of experience with this, it is hardly surprising that they use many of the design techniques they have employed for their HAPS and ChipIt products as recommendations for users that choose to roll their own. Clearly, when you make your own, you will not need quite the same level of configurability, but there are many useful lessons.

Chapter 6 is the flip side of the previous chapter and talks about ready-made prototyping systems. As expected it concentrates on modularity and extensibility, one of the prime differentiators of the Synopsys prototyping system.

Chapter 7 gets down and dirty with the steps necessary to prepare a design and things that are common to an SoC flow that do not work for FPGAs. It says the unmentionable that at some point changes to the RTL will be necessary. The honesty in this book is actually quite refreshing. It discusses the issues associated with clock gating and memories and tells you which cases will require some manual intervention plus the best practices for maintaining a common set of source files. It also talks about features that just cannot be mapped into a prototype such as some power-saving capabilities being increasingly used in SoCs.

That was all I had time to read, but the remaining chapters focus on the following topics:

• Chapter 8 Partitioning and reconnecting
• Chapter 9 Design-for-Prototyping
• Chapter 10 IP and High-Speed Interfaces
• Chapter 11 Bring up and debug: the prototype in the lab
• Chapter 12 Breaking out of the lab: the prototype in the field
• Chapter 13 Prototyping and Verification = The best of both worlds
• Chapter 14 The future of prototyping
• Chapter 15 Conclusions

The book also contains two appendixes:

• Appendix A Worked example from Texas Instruments
• Appendix B Economics of making prototype boards

The almost 500 page book is free if your happen to have a SolvNet login, which basically means you are a Synopsys customer, otherwise it is a reasonable $9.99 for a Kindle edition or $49.99 for a print copy. Click Here for the download page.

Some nits with the book. For the online version of the book, there is no added expense of using color, and some of the diagrams were created expecting color. So diagrams such as Figure 3 become almost impossible to read in grey-scale because it is impossible to match to the key. In addition, there is no cost to hyper-linking the document such that references are available at the click of a button. This improves general navigation and also makes it possible to dive into topics without losing the general flow. Also, and this may not be a fair criticism since I reviewed a draft copy of the book, there are quite a few places where the editing has been lax – still none are bad enough to prevent the meaning from coming through.

In conclusion, this book is highly worth the read (even though there is a lot of the book that I have not yet covered). The parts I have read show that the authors do have extensive knowledge and experience of the subject matter and the information is well presented, so this book receives a definite two thumbs up from me!

Brian Bailey – keeping you covered