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Cadence adds virtual models and FPGA prototyping to System Development Suite
Mike Demler
5/9/2011 12:38 PM EDT
Cadence made quite the big splash entrance as a first-time exhibitor at the Silicon Valley Embedded Systems Conference on Tuesday, May 3rd, holding a perhaps unprecedented (certainly for EDA) press conference on the exhibit floor to announce what they described as "A Breakthrough in System Development". The event started with a long digression into the world of tablet mania and mobile apps by CMO John Bruggeman, which took up most of what had been scheduled as a 30 minute session. Nimish Modi (Senior VP for the System Realization Group) then followed with a brief description of the core announcement - two new platforms for the company's suite of system development tools. Cadence is adding an FPGA-based rapid prototyping system, and a virtual system modeling platform. With these two new platforms, Cadence "promises to cut system integration time by up to half for next-generation designs, according to the company's press release.
The claimed "breakthroughs" in Cadence's System Development Suite are actually neither new or unique, but they do strengthen the company's offering in order to better compete with Synopsys. Synopsys established themselves in this space through a series of acquisitions in recent years; in the FPGA-prototyping space (2008 - Synplicity, now HAPS), and in virtual platform solutions (2006 - Virtio and 2010 - VAST). Cadence can now offer their own complete system design flow, which includes the Incisive Verification platform (a competitor to Synopsys' Discovery platform) and hardware acceleration and emulation with Palladium in the Verification Computing Platform. Synopsys lacks emulation but has worked closely with EVE on this part of their solution, leading some experts to speculate on the potential of another acquisition.
Now, in Cadence's System Development Suite, designers can use Palladium or Palladium-XP to accelerate verification of their designs prior to executing the FPGA prototype place & route step. Cadence specifies the Rapid Prototyping Platform for a capacity of up to 30 million ASIC gates, and the tools are capable of automatically partitioning your design to multiple FPGAs, according to Michal Siwinski (Sr. Director, Solution & Product Marketing). According to the Rapid Prototyping Platform datasheet, you can configure the hardware with from 2-6 Altera Stratix-4 8SE820-3 FPGAs, providing up to 5M ASIC gates capacity (design-dependent) and 33,294 Kbits of embedded memory per FPGA. As a comparison; Synopsys uses Xilinx Virtex®-6 LX760 FPGAs, and claims to be capable of supporting designs up to 81 million ASIC gates.
For customers who use the Palladium products; Cadence is emphasizing that you can take advantage of compatibility with the Palladium language set (synthesizable constructs only), scripting and setup files, and clock definition files. You can use the Cadence HDL (hardware description language) ICE (in-circuit emulator) to map your design to the FPGAs while maintaining your RTL constructs. By utilizing the common environment with the Verification Computing Platform, you can connect to real-world interfaces with Cadence's family of SpeedBridge adapters. With a SpeedBridge, as the name indicates, you are able to buffer slower speed data from your FPGA-prototype or emulation model to the higher speeds required to test real-world I/O such as for USB, ethernet, and PCI standards.
Cadence's Siwinski describes the Virtual System Platform as a software development platform that is built on top of abstracted hardware models. The emphasis is on linking TLM with RTL, which has already available in the Incisive simulator. (Synopsys has also done this previously with EVE). Designers can perform mixed TLM/RTL simulation, and you can take advantage of the common metric-driven verification methodology with the Incisive Verification Platform to reduce discrepancies between the abstracted hardware model and the eventual RTL. The System Development Suite also provides a single debugger that you can use for both hardware and software development - based on Cadence's SimVision product.
Siwinski says that a tool in the Virtual System Platform enables users to create TLM models "semi-automatically". You just need to define registers or memory based on IEEE 1685 IP-XACT or register-description languages for non-processor models. For processor models, Cadence is collaborating with 3rd party IP vendors, such as ARM and others. The Virtual Platform includes features to ease debugging for multi-core designs such as ARM's A9, enabling you to create processor-specific breakpoints and implement software execution control.
The Cadence Virtual System Platform is in an early adopter phase, and the company is planning for a general release later this year. The Rapid Prototyping Platform was initially released late last year, and is now in production for both the hardware and software components.
Now, in Cadence's System Development Suite, designers can use Palladium or Palladium-XP to accelerate verification of their designs prior to executing the FPGA prototype place & route step. Cadence specifies the Rapid Prototyping Platform for a capacity of up to 30 million ASIC gates, and the tools are capable of automatically partitioning your design to multiple FPGAs, according to Michal Siwinski (Sr. Director, Solution & Product Marketing). According to the Rapid Prototyping Platform datasheet, you can configure the hardware with from 2-6 Altera Stratix-4 8SE820-3 FPGAs, providing up to 5M ASIC gates capacity (design-dependent) and 33,294 Kbits of embedded memory per FPGA. As a comparison; Synopsys uses Xilinx Virtex®-6 LX760 FPGAs, and claims to be capable of supporting designs up to 81 million ASIC gates.
For customers who use the Palladium products; Cadence is emphasizing that you can take advantage of compatibility with the Palladium language set (synthesizable constructs only), scripting and setup files, and clock definition files. You can use the Cadence HDL (hardware description language) ICE (in-circuit emulator) to map your design to the FPGAs while maintaining your RTL constructs. By utilizing the common environment with the Verification Computing Platform, you can connect to real-world interfaces with Cadence's family of SpeedBridge adapters. With a SpeedBridge, as the name indicates, you are able to buffer slower speed data from your FPGA-prototype or emulation model to the higher speeds required to test real-world I/O such as for USB, ethernet, and PCI standards.
Cadence's Siwinski describes the Virtual System Platform as a software development platform that is built on top of abstracted hardware models. The emphasis is on linking TLM with RTL, which has already available in the Incisive simulator. (Synopsys has also done this previously with EVE). Designers can perform mixed TLM/RTL simulation, and you can take advantage of the common metric-driven verification methodology with the Incisive Verification Platform to reduce discrepancies between the abstracted hardware model and the eventual RTL. The System Development Suite also provides a single debugger that you can use for both hardware and software development - based on Cadence's SimVision product.
Siwinski says that a tool in the Virtual System Platform enables users to create TLM models "semi-automatically". You just need to define registers or memory based on IEEE 1685 IP-XACT or register-description languages for non-processor models. For processor models, Cadence is collaborating with 3rd party IP vendors, such as ARM and others. The Virtual Platform includes features to ease debugging for multi-core designs such as ARM's A9, enabling you to create processor-specific breakpoints and implement software execution control.
The Cadence Virtual System Platform is in an early adopter phase, and the company is planning for a general release later this year. The Rapid Prototyping Platform was initially released late last year, and is now in production for both the hardware and software components.
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