Blog
Comment
Max the Magnificent
Re the beginning of this article where I couldn't think of a politically correct ...
Free Webinar: Prototyping multi-million-gate ASIC designs
Clive Maxfield
7/19/2011 1:03 PM EDT
Good Grief. I don’t know about you, but I’m busier than a … well, a person who is very, very busy (I can’t think of a “politically correct” simile – the ones that pop into my mind would get me into trouble [grin]).
For example, I just received a message about a Free Webinar that’s being held this coming Thursday at 11:00 a.m. Pacific Time (that’s 2:00 p.m. Eastern time). (Click Here for more information and to register.)
The theme of this webinar is FPGA-based prototyping of large ASICs and SoCs. “Hmmm,” I thought, “that sounds interesting.” So I checked my calendar to see if I would be available to attend… only to discover that I’m already booked… as the moderator of this webinar!
I’m obviously juggling too many balls in the air at the moment… and the problem is that I can’t juggle (well, I do say that I can juggle with five expensive porcelain plates, but only for a very short period of time [grin]).
Anyway, the official description for this webinar is as follows (this is an interactive event where you can post questions to the presenter – hopefully I will “see” you there)”
Overview:
Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug, and development for much larger SoC projects than ever before. The webinar introduces this new addition to the HAPS family and provides an overview of the complete solution, which includes integrated and scalable hardware plus comprehensive software tool flow. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.
What attendees will learn:
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
For example, I just received a message about a Free Webinar that’s being held this coming Thursday at 11:00 a.m. Pacific Time (that’s 2:00 p.m. Eastern time). (Click Here for more information and to register.)
The theme of this webinar is FPGA-based prototyping of large ASICs and SoCs. “Hmmm,” I thought, “that sounds interesting.” So I checked my calendar to see if I would be available to attend… only to discover that I’m already booked… as the moderator of this webinar!
I’m obviously juggling too many balls in the air at the moment… and the problem is that I can’t juggle (well, I do say that I can juggle with five expensive porcelain plates, but only for a very short period of time [grin]).
Anyway, the official description for this webinar is as follows (this is an interactive event where you can post questions to the presenter – hopefully I will “see” you there)”
Overview:
Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug, and development for much larger SoC projects than ever before. The webinar introduces this new addition to the HAPS family and provides an overview of the complete solution, which includes integrated and scalable hardware plus comprehensive software tool flow. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.
What attendees will learn:
- How to implement a multi-million ASIC gate design into a multi-FPGA-based prototyping system by using a semi-automated flow and flexible hardware interconnect architecture
- How to use co-simulation for quicker system bring-up
- How to debug a design over multiple FPGAs
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
|
|
|
|
|
Navigate to related information
Max the Magnificent
7/19/2011 1:12 PM EDT
Re the beginning of this article where I couldn't think of a politically correct simile for being busy...
You know the type of thing: "Busier than a ..."
Although my hands are tied, I would be more than happy to hear your suggestions...
Sign in to Reply