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iniewski
Deepak, congrats, very interesting article...there is one more class of ...
Viewpoint: What lies ahead for on-chip interconnect technology?
Deepak Sekar, MonolithIC 3D
9/19/2011 1:25 PM EDT
During his 2011 VLSI Symposium keynote, Sam Naffziger, an AMD Corporate Fellow showed the slide illustrated in Figure 1 and said:
"We are at the cusp of a dramatic increase in on-chip wire RC delays due to a number of factors such as small geometries resulting in increased edge effect scattering, the lack of dielectric improvement and the overhead from copper cladding layers. This trend will seriously reduce both the density and performance benefits of process scaling, so some sort of revolutionary improvement in on-chip interconnect is required."
Sam Naffziger was talking about logic technologies. For memory, the situation could be even worse. For a NAND flash memory chip, for instance, all bit-lines can be 10mm long and 24nm wide. The performance of the memory array is dominated by RC delay of wires.
This raises a question: What are the technological options available for improving on-chip interconnects? Let’s take a look…
Silver interconnects
Silver is the only well-known metal with higher bulk conductivity (5.6% higher) than copper. At small feature sizes though, silver loses much of this advantage, due to higher scattering effects than copper. Silver is harder to process than copper as well. Silver is therefore not considered a viable replacement to copper: The benefits of silver over copper are negligibly small (if any) and it costs too much.
Carbon-based interconnects
Carbon nanotubes (CNTs) and graphene offer lower resistivity than copper. This is reflected in CNTs having mean free paths in the um range and graphene having mean free paths in the 100s of nm range; compared to 40nm for copper. Carbon-based interconnects are more resistive to electromigration and have higher thermal conductivity than copper too. However, getting low contact resistance, sub-400C growth and low defect density are unsolved issues for both CNTs and graphene. Growth of horizontally-oriented CNTs is known to be very challenging as well. These are early days for carbon-based interconnect technology. The research community is actively exploring solutions to these issues.
3D with Through-Silicon Via (TSV) technology
We are starting to see this exciting technology move into production today. The most promising applications at the moment seem to be 3D stacked wide I/O DRAM chips and stacking DRAM atop logic. Figure 2 shows the roadmap for TSV technology from the International Technology Roadmap for Semiconductors (ITRS). Minimum TSV dimensions are 1um or so. It is somewhat difficult to reduce TSV dimensions below the 500nm-1um range due to misalignment issues from bonding and due to thickness of stacked silicon layers being in the 10um range for cost-effective manufacturing, as the ITRS roadmap suggests. Because of the large size of TSVs (1um) compared to on-chip wires (20-40nm), many argue that it is difficult to move a significant percentage of on-chip wires into the third dimension. This being said, there is widespread consensus that TSV technology dramatically reduces chip-to-chip interconnect problems. For example, wire length between DRAM and logic chips reduces dramatically with TSVs.
Monolithic 3D
With monolithic 3D logic technologies, the goal is to make high-quality single crystal silicon transistors monolithically atop copper/low k interconnect levels. This results in through-silicon connections being around the same size as horizontal wires (~20-40nm). The benefits of 3D routing can therefore be applied to all wires on the chip, and need not apply to just a few wires on the top two metal levels. This could provide significant benefits to chip power, performance and die size. A recent EDN article titled “3D-ICs without TSVs?” gives details of how this technology can be implemented, and lists some pros and cons.
While Monolithic 3D is just starting to appear on logic technologists’ radar screens, it has gained significant traction in the non-volatile memory industry. Toshiba, Samsung, SanDisk and Micron have monolithic 3D on their roadmap within the next four years. Flash memory makers scale the fastest in our industry. They seem to have hit the limits of lithographic scaling first, and have settled on monolithic 3D as an alternative. Will the logic and DRAM industries follow suit?
Air gap dielectrics
Air-gap dielectrics can provide an effective dielectric constant of 2.2-2.5, according to the ITRS. These compare with effective dielectric constants of 2.5-2.8 possible today with porous low k dielectrics. Figure 3 shows two different air-gap schemes. Many of my friends in the logic industry are skeptical of air gaps going into production due to mechanical stability issues... I disagree with them though. Several NAND flash memory manufacturers are shipping products based on air gap technology today (see Figure 3). These NAND flash makers did the air-gap development without too much fuss. Although the memory world is different from logic, I believe the logic industry will eventually take air gaps into production as well.
Optical interconnects
For some of the longest interconnects on the chip, optical links might give better performance than copper, when Wavelength Division Multiplexing (WDM) is used. However, for this scenario to occur, one requires on-chip optical modulators, detectors and waveguides, which add additional masks, process steps and cost. These components currently take a lot of die area as well. Several factors are unclear, such as, for example: (1) Is having an off-chip optical source, such as a laser, viable in terms of cost and complexity? (2) Can light be bent within reasonable distances for on-chip routing? Based on analyses from Intel, IMEC and others, many experts believe the benefits of optical interconnects for on-chip applications are not worth the complexity and cost they add, at least for the next 5-10 years.
I’ll end this article with an interesting comment made by Mark Bohr, a Senior Fellow at Intel, at the 2010 International Interconnect Technology Conference. He said, “There are many solutions for improving transistors, but there aren't many options for improving interconnects. We need you, the interconnect community, to find and develop these solutions.” It looks like an interesting next decade for interconnect technologists. They have a lot of work to do!
About the author
Dr. Deepak Sekar received a B. Tech from the Indian Institute of Technology (Madras) in 2003 and a PhD from the Georgia Institute of Technology in 2008. He worked at SanDisk Corporation between 2006 and 2010, and conducted research on non-volatile memory. He joined MonolithIC 3D Inc. in early-2010 as a Principal Engineer, and is now the Chief Scientist of the company.
For the past 8 years, Dr. Sekar's research has focused on 3D Integrated Circuits. His PhD research involved doing some of the first experimental work on microchannel cooled 3D stacked chips. He also developed a CAD tool called IntSim that simulates 2D and 3D stacked systems. At SanDisk, Dr. Sekar worked in the area of 3D crosspoint memory and developed rewritable memory devices, selector diodes and array architectures. He received two awards from SanDisk for this work.
Dr. Sekar is the author of a book, an invited book chapter, 15 publications and 55 issued or pending patents, predominantly in the field of 3D integration. Awards he has received include a Best Student Paper Award at the Intl. Interconnect Technology Conference (2008), a Best Paper Award at the IETE Technical Review (2009), an Intel PhD Fellowship (2006-2008), a Motorola Electronic Packaging Fellowship Award at the Electronic Components and Technology Conference (2008), two Inventor Recognition Awards from the Semiconductor Research Corporation (2006, 2009) and the National Talent Scholarship from the Government of India (1997-2003). He serves as a Program Committee Co-Chair at the Intl. Interconnect Technology Conference.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
"We are at the cusp of a dramatic increase in on-chip wire RC delays due to a number of factors such as small geometries resulting in increased edge effect scattering, the lack of dielectric improvement and the overhead from copper cladding layers. This trend will seriously reduce both the density and performance benefits of process scaling, so some sort of revolutionary improvement in on-chip interconnect is required."
Sam Naffziger was talking about logic technologies. For memory, the situation could be even worse. For a NAND flash memory chip, for instance, all bit-lines can be 10mm long and 24nm wide. The performance of the memory array is dominated by RC delay of wires.
This raises a question: What are the technological options available for improving on-chip interconnects? Let’s take a look…
Figure 1
Silver interconnects
Silver is the only well-known metal with higher bulk conductivity (5.6% higher) than copper. At small feature sizes though, silver loses much of this advantage, due to higher scattering effects than copper. Silver is harder to process than copper as well. Silver is therefore not considered a viable replacement to copper: The benefits of silver over copper are negligibly small (if any) and it costs too much.
Carbon-based interconnects
Carbon nanotubes (CNTs) and graphene offer lower resistivity than copper. This is reflected in CNTs having mean free paths in the um range and graphene having mean free paths in the 100s of nm range; compared to 40nm for copper. Carbon-based interconnects are more resistive to electromigration and have higher thermal conductivity than copper too. However, getting low contact resistance, sub-400C growth and low defect density are unsolved issues for both CNTs and graphene. Growth of horizontally-oriented CNTs is known to be very challenging as well. These are early days for carbon-based interconnect technology. The research community is actively exploring solutions to these issues.
3D with Through-Silicon Via (TSV) technology
We are starting to see this exciting technology move into production today. The most promising applications at the moment seem to be 3D stacked wide I/O DRAM chips and stacking DRAM atop logic. Figure 2 shows the roadmap for TSV technology from the International Technology Roadmap for Semiconductors (ITRS). Minimum TSV dimensions are 1um or so. It is somewhat difficult to reduce TSV dimensions below the 500nm-1um range due to misalignment issues from bonding and due to thickness of stacked silicon layers being in the 10um range for cost-effective manufacturing, as the ITRS roadmap suggests. Because of the large size of TSVs (1um) compared to on-chip wires (20-40nm), many argue that it is difficult to move a significant percentage of on-chip wires into the third dimension. This being said, there is widespread consensus that TSV technology dramatically reduces chip-to-chip interconnect problems. For example, wire length between DRAM and logic chips reduces dramatically with TSVs.
Figure 2
Monolithic 3D
With monolithic 3D logic technologies, the goal is to make high-quality single crystal silicon transistors monolithically atop copper/low k interconnect levels. This results in through-silicon connections being around the same size as horizontal wires (~20-40nm). The benefits of 3D routing can therefore be applied to all wires on the chip, and need not apply to just a few wires on the top two metal levels. This could provide significant benefits to chip power, performance and die size. A recent EDN article titled “3D-ICs without TSVs?” gives details of how this technology can be implemented, and lists some pros and cons.
While Monolithic 3D is just starting to appear on logic technologists’ radar screens, it has gained significant traction in the non-volatile memory industry. Toshiba, Samsung, SanDisk and Micron have monolithic 3D on their roadmap within the next four years. Flash memory makers scale the fastest in our industry. They seem to have hit the limits of lithographic scaling first, and have settled on monolithic 3D as an alternative. Will the logic and DRAM industries follow suit?
Air gap dielectrics
Air-gap dielectrics can provide an effective dielectric constant of 2.2-2.5, according to the ITRS. These compare with effective dielectric constants of 2.5-2.8 possible today with porous low k dielectrics. Figure 3 shows two different air-gap schemes. Many of my friends in the logic industry are skeptical of air gaps going into production due to mechanical stability issues... I disagree with them though. Several NAND flash memory manufacturers are shipping products based on air gap technology today (see Figure 3). These NAND flash makers did the air-gap development without too much fuss. Although the memory world is different from logic, I believe the logic industry will eventually take air gaps into production as well.
Figure 3
Optical interconnects
For some of the longest interconnects on the chip, optical links might give better performance than copper, when Wavelength Division Multiplexing (WDM) is used. However, for this scenario to occur, one requires on-chip optical modulators, detectors and waveguides, which add additional masks, process steps and cost. These components currently take a lot of die area as well. Several factors are unclear, such as, for example: (1) Is having an off-chip optical source, such as a laser, viable in terms of cost and complexity? (2) Can light be bent within reasonable distances for on-chip routing? Based on analyses from Intel, IMEC and others, many experts believe the benefits of optical interconnects for on-chip applications are not worth the complexity and cost they add, at least for the next 5-10 years.
I’ll end this article with an interesting comment made by Mark Bohr, a Senior Fellow at Intel, at the 2010 International Interconnect Technology Conference. He said, “There are many solutions for improving transistors, but there aren't many options for improving interconnects. We need you, the interconnect community, to find and develop these solutions.” It looks like an interesting next decade for interconnect technologists. They have a lot of work to do!
About the author
Dr. Deepak Sekar received a B. Tech from the Indian Institute of Technology (Madras) in 2003 and a PhD from the Georgia Institute of Technology in 2008. He worked at SanDisk Corporation between 2006 and 2010, and conducted research on non-volatile memory. He joined MonolithIC 3D Inc. in early-2010 as a Principal Engineer, and is now the Chief Scientist of the company. For the past 8 years, Dr. Sekar's research has focused on 3D Integrated Circuits. His PhD research involved doing some of the first experimental work on microchannel cooled 3D stacked chips. He also developed a CAD tool called IntSim that simulates 2D and 3D stacked systems. At SanDisk, Dr. Sekar worked in the area of 3D crosspoint memory and developed rewritable memory devices, selector diodes and array architectures. He received two awards from SanDisk for this work.
Dr. Sekar is the author of a book, an invited book chapter, 15 publications and 55 issued or pending patents, predominantly in the field of 3D integration. Awards he has received include a Best Student Paper Award at the Intl. Interconnect Technology Conference (2008), a Best Paper Award at the IETE Technical Review (2009), an Intel PhD Fellowship (2006-2008), a Motorola Electronic Packaging Fellowship Award at the Electronic Components and Technology Conference (2008), two Inventor Recognition Awards from the Semiconductor Research Corporation (2006, 2009) and the National Talent Scholarship from the Government of India (1997-2003). He serves as a Program Committee Co-Chair at the Intl. Interconnect Technology Conference.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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iniewski
1/6/2012 11:38 AM EST
Deepak, congrats, very interesting article...there is one more class of potential interconnect strategy: wireless...this approach has been pursued by few academics and obviously adding some RF transceivers on chip to propagate signals is a heavy overhead but for completeness perhaps that approach should be mentioned...Kris
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