Well, today we certainly do have some exciting news, because Altera
have just announced two new families of ARM-based SoC FPGAs implemented at the 28nm node.
It’s funny how things come and go over the years. In the not-so-distant past, Altera fielded a line of FPGAs with an embedded hard-core ARM processor … and nobody really came to the party.
There are a number of possible reasons why these original offerings failed to excite interest. Personally I think they were ahead of their time – the vast majority of designers still thought in terms of having an off-the-shelf processor chip on the board and then connecting that processor to a separate FPGA.
Thus, the folks at Altera turned away from embedding hard core processors in their FPGAs and instead focused their attention on their 32-bit Nios soft processor core. But the times they are a-changing… today, the majority of FPGA designs include one or more processors, and everyone needs more bandwidth and performance, so the time is ripe to reintroduce a hard core processor into the FPGA fabric.
And we’re not talking about any old weedy processor here. What we’re talking about is a dual-core ARM Cortex-A9 in which each core has dedicated L1 instruction and data caches and both cores share an L2 cache, and hard memory controller, and a bunch of hard peripherals. Basically, this provides enough processing power and data bandwidth to bring tears of joy to the grumpiest of designers.
But wait, there’s more, because Altera are also introducing what they exuberantly describe as “The FPGA Industry’s First Virtual Target.”
What they are talking about here is a virtual prototyping environment that is binary and register-compatible with the physical FPGA, which allows the software developers to immediately start performing their magic.
Now, it’s important to note that this virtual target encompasses the ARM Cortex-A9 and peripherals, along with hard interface functions like Ethernet and USB, and DDR and Flash memory controllers. The point is that the virtual target does not encompass the programmable FPGA fabric – however the environment does support "FPGA-in-the-loop". This means that the programmable fabric portion of the design can be implemented in a physical FPGA, and this physical FPGA then communicates with the virtual prototype of the ARM Cortex-A9 etc.
You can read much more about today’s announcements in Collin Holland’s excellent columns: Altera integrated ARP processor in FPGAs
and Virtual target eases software development
. Also, Click Here
to access a PDF containing a more detailed overview of these new devices.
One thing that interests me is the difference in the way Altera are positioning these new devices as compared to Xilinx with their 28nm Zynq devices
, which also feature a dual core ARM Cortex-A9.
Xilinx are targeting their Zynq devices at software developers. They don’t even mention the term “FPGA” in any of their diagrams. Instead they refer to the FPGA fabric as “Extensible” fabric. The idea is that if the software developers require access to something like a hardware accelerator, they hand this task off to their FPGA designer colleagues who “make it happen”.
It’s easy to see the advantage of the Xilinx approach – software developers just think about the chip as a regular dual core ARM Cortex-A9 processor whose performance can be enhanced “behind the scenes.” [My description here is, of course, a very simplistic way of looking at things – but I’m a simple man (grin).]
By comparison, the folks at Altera are coming at things from a completely different direction saying “This is an SoC FPGA that – in addition to programmable fabric – also contains a dual core ARM Cortex-A9 processor.”
What I would really like is to chat to some end users and see which of these approaches they prefer… having said this, I would be happy to bet that both approaches will find their proponents and detractors…
I LOVE this stuff!!!
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