Space Codesign Systems
has announced support for ARM‐based FPGA design in its SpaceStudio™ 2.2 virtual platform technology. While we have seen similar announcements from Cadence with Xilinx and Synopsys with Altera recently, Space goes further in that this is not just a virtual prototype, but a full hardware/software codesign solution. I spoke with Gary Dare, VP of technical marketing for Space. He said “Space Codesign looks at both hardware and software, and automates the partitioning process in hardware/software co-design. Rather than involve separate hardware and software IP for the same function (which also raises the question of whether they are really the same (i.e., equivalence)). With Space Codesign, there is no recoding when you move a function (IP) between hardware (implemented as circuitry) and software (running on a processor).”
In their press release they said: SpaceStudio™ 2.2’s virtual platform technology features new libraries with the ARM Cortex‐A9 dual MPCore processor and AMBA bus architecture that will be useful for the ESL design implementation of the upcoming Xilinx Zynq (Extensible Processing Platform) family. Tailored to system architects and software developers, SpaceStudio™ 2.2 will serve as a comprehensive Electronic System Level (ESL) tool that covers the early and middle System On Chip (SoC) design cycle.
This got me to thinking about the partitioning process, because it is not just about hardware/software partitioning, it is also software/software partitioning with the multiple processor cores. Gary had this to say: "Designers can create an initial architecture and then start exploring the design space. Hardware/software partitioning is supported by the ability to move hardware IP's from an interconnect to a processor - and vice-versa. The same SystemC module that might have been implemented as hardware can run as a processor-based application in your final embedded system with the use of our special porting libraries. In a multicore scenario, software/software partitioning is carried out by reallocating functions between processors to balance loads and/or improve performance. In a multiple bus or network-on-chip architecture, hardware/hardware partitioning involves moving hardware functions from one channel to another. To help the engineer make such decisions, we provide Space-Monitor for seamless and non-intrusive performance profiling."
Finally, I asked Gary to define how this would fit into a complete ESL flow. His answer:
First, functional specification is carried out using SpaceStudio’s Elix module, working at a high level of abstraction prior to committing system functions to either hardware or software. Communication between blocks can be specified and functional validation of specifications carried out by generating executable models of the system to perform untimed or timed functional simulations.
Next, the system’s architecture is created in SpaceStudio’s Simtek module, using component libraries (our SpaceLib, as well as user's own or third party IP) and the mapping of Elix-validated functional blocks to the architecture’s components.
"Then design exploration is conducted, with performance profiling through our Space-Monitor, until the engineer is satisfied with their final architecture. For implementation of the hardware portion of the system, SpaceStudio’s GenX module generates and integrates the required hardware IPs, glue logic, firmware, embedded software, configuration files and parameters to implement the chosen system design into the final target using a standard downstream RTL flow for FPGA or ASIC.
As far as I know, Space is the only hardware/software codesign tool on the market. Ten years ago, it was the hot topic of research and even Cadence was peddling a solution to this problem, which was sold to CoWare, that got bought by Synopsys and somewhere along the line this capability disappeared.Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).