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Predictions for 2012: ESL
Brian Bailey
1/16/2012 7:27 PM EST
A couple of weeks ago I sent out a call for predictions related to EDA, IP and semiconductor industry companies. I received 24 predictions from 11 companies and I would like to thank all of them and the PR people who worked so hard to get them to me. I have divided the predictions into a number of categories: those related to industry trends, tools, ESL, IP and physical. As for myself, I will follow the Chinese proverb: a wise man once said nothing.
Last week, I presented those predictions that fell into the industry trends and tools categories. Today we look at a special category of tools, namely those in the emerging ESL area.
Shawn McCloud, Calypto Design Systems V.P. Marketing
High-level synthesis (HLS) technologies are becoming more main stream, and this trend will continue in 2012. Power optimization will become a key motivation for adopting HLS as 32 nm technology ushers in dramatic increases in power density, affecting battery life as well as thermal and supply integrity. The first HLS-ready virtual platforms will be deployed on production designs, bringing with them the advantages of TLM Synthesis and single source modeling for TLM 2.0 and HLS. C to RTL formal equivalence tools will become an integral and familiar part of HLS flows, reducing the verification effort. And SystemC will be enhanced to support high-speed, transaction-level verification in the context of HLS implementation flows.
Paul van Besouw President and CEO Oasys Design Systems
The big issue in 2012 will continue to be power. The big challenge in designing an SoC is whether the entire chip can be lit up at once (answer "no") and what to do about it. Multicore processors make this problem much worse since there is no point in putting an extra core on a chip unless it can also be turned on at the same time as all the other cores. Otherwise, why bother? Power has to be addressed at the architectural level, although there are certainly things that can be done downstream in the design flow to make incremental improvement. Power is a chip-level problem and needs to be addressed at the chip level.
Adnan Hamid Chief Executive Officer Breker Verification Systems
Dominance in low-power SoC performance will be a key battlefield in 2012 and will push the limits of existing verification techniques. Low power isn't just about portable devices any more. The quest for lower power spans almost all application segments. SoC devices are the key building blocks for many of the fastest growing market segments and the large semiconductor manufacturers are locked in battle to deliver the highest performance/lowest power SoCs. There are already automation tools available to design, implement and analyze complex on-chip power management systems, but a complete lack of automated tools for verifying these systems in the context of the SoC functionality. A new methodology for automating SoC system-level verification will emerge in 2012 that will directly address the verification of complex SoC power management systems.
Mentor ESL and Functional Verification
Technology and economics drive the move up in abstraction from chip design to system design and from RTL to high-level synthesis (HLS). Abstraction, by itself, has limited value, but automation unlocks its full potential. While HLS delivers automation in design, it also pushes verification abstraction past TLM, opening new verification automation opportunities. In addition, the past decade has demonstrated the importance of reuse. While verification reuse has lagged design reuse, it is catching up through standards like UVM and TLM 2.0. In the near future, SoCs will achieve 90% design reuse and see double-digit growth in verification reuse.
Please feel free to add your own predictions by leaving a comment...
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Last week, I presented those predictions that fell into the industry trends and tools categories. Today we look at a special category of tools, namely those in the emerging ESL area.
Shawn McCloud, Calypto Design Systems V.P. Marketing
High-level synthesis (HLS) technologies are becoming more main stream, and this trend will continue in 2012. Power optimization will become a key motivation for adopting HLS as 32 nm technology ushers in dramatic increases in power density, affecting battery life as well as thermal and supply integrity. The first HLS-ready virtual platforms will be deployed on production designs, bringing with them the advantages of TLM Synthesis and single source modeling for TLM 2.0 and HLS. C to RTL formal equivalence tools will become an integral and familiar part of HLS flows, reducing the verification effort. And SystemC will be enhanced to support high-speed, transaction-level verification in the context of HLS implementation flows.
Paul van Besouw President and CEO Oasys Design Systems
The big issue in 2012 will continue to be power. The big challenge in designing an SoC is whether the entire chip can be lit up at once (answer "no") and what to do about it. Multicore processors make this problem much worse since there is no point in putting an extra core on a chip unless it can also be turned on at the same time as all the other cores. Otherwise, why bother? Power has to be addressed at the architectural level, although there are certainly things that can be done downstream in the design flow to make incremental improvement. Power is a chip-level problem and needs to be addressed at the chip level.
Adnan Hamid Chief Executive Officer Breker Verification Systems
Dominance in low-power SoC performance will be a key battlefield in 2012 and will push the limits of existing verification techniques. Low power isn't just about portable devices any more. The quest for lower power spans almost all application segments. SoC devices are the key building blocks for many of the fastest growing market segments and the large semiconductor manufacturers are locked in battle to deliver the highest performance/lowest power SoCs. There are already automation tools available to design, implement and analyze complex on-chip power management systems, but a complete lack of automated tools for verifying these systems in the context of the SoC functionality. A new methodology for automating SoC system-level verification will emerge in 2012 that will directly address the verification of complex SoC power management systems.
Mentor ESL and Functional Verification
Technology and economics drive the move up in abstraction from chip design to system design and from RTL to high-level synthesis (HLS). Abstraction, by itself, has limited value, but automation unlocks its full potential. While HLS delivers automation in design, it also pushes verification abstraction past TLM, opening new verification automation opportunities. In addition, the past decade has demonstrated the importance of reuse. While verification reuse has lagged design reuse, it is catching up through standards like UVM and TLM 2.0. In the near future, SoCs will achieve 90% design reuse and see double-digit growth in verification reuse.
Please feel free to add your own predictions by leaving a comment...
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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