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Predictions for 2012: IP and Physical Design
Brian Bailey
1/20/2012 2:05 PM EST
A couple of weeks ago I sent out a call for predictions related to EDA, IP and semiconductor industry companies. I received 24 predictions from 11 companies and I would like to thank all of them and the PR people who worked so hard to get them to me. I have divided the predictions into a number of categories: those related to industry trends, tools, ESL, IP and physical. As for myself, I will follow the Chinese proverb: a wise man once said nothing.
Today, I wrap up this mini-series by presenting the predictions in the areas of IP and physical design.
IP
Bill Neifert Chief Technology Officer Carbon Design Systems
Time to market pressures will force more IP sales to instead become subsystems sales
This is a trend we’ve seen with design teams over the past year or so which is gaining more and more momentum. The increasing complexity of individual IP blocks means that when multiple blocks are integrated together it’s more and more difficult to tie them all together well in an optimal configuration, especially where software is involved. It makes much more sense to buy the entire, configured subsystem from a single vendor and just make minor configuration tweaks to the provided hardware and software.
Ed Bard, Sr. Director of Marketing, Digital IP, Memories, Logic Libraries, FPGA Prototyping & Synthesis at Synopsys.
Complete, pre-validated subsystems will hit the IP market as the next evolution in the IP business. Unlike the traditional view of SoC IP, which is hardware centric and delivered as RTL or GDSII, subsystems consist of pre-integrated hardware, software and prototypes that are SoC-ready, meaning designers can just drop it in and go. As more functionality gets integrated into today’s designs, having multiple, integrated IP blocks that are verified and optimized for a specific function will enable designers to significantly reduce integration effort. In the end, what differentiates the IP subsystem will be the software and prototyping capabilities, allowing engineers to accelerate their development cycle by addressing their challenges at a system-level, rather than the block-level.
Physical Issues
Paul van Besouw President and CEO Oasys Design Systems
A big issue for 2012 will be noise. Signal voltages are now down close to the noise voltages, which often don't scale with the power supply at all. We are also getting closer to having to worry about counting atoms. After all, a 20nm gate is 200 hydrogen atoms across, or about 80 copper atoms, never mind how few atoms make up a gate oxide. Creating and analyzing physical design must be done at as high a level as possible, ideally at the chip level.
Paul van Besouw President and CEO Oasys Design Systems
At 65nm, the big issue facing designers was whether Joe Costello could be lured back into EDA if he was allowed to dress as a rock star. By 45nm, Apple had decided to move into IC design and make its own semiconductors, so the big question was whether Mac was superior to PC. At 32nm lithography issues dominated and the big question was whether it was possible to surf 193nm light waves to working silicon, going big and really small at the same time. For 2012 and for 28-22nm design, the big question remains to be defined but for sure will be on video in June. Editor note: hmmm, now what could that imply?
Mentor Design to Silicon group
IBS Inc. states that 28nm designs starts will increase by 50% over 2011, while current 28nm designs will be ramping to full production. We project this will cause fabless companies to seek second sources foundries to satisfy demand, driving additional 28nm design efforts. We expect increases in the number of 20nm test chips in 2012, with the first full reticle design tape outs in 2013. At 20nm, foundries will introduce cell-based “smart fill” techniques to reduce file size and DRC run times. Double patterning for 20nm will require more extraction corners, creating demand for faster, multi-CPU extraction tools. Thinner gate oxides and multi-voltage designs will require more rigorous circuit checking to avoid delayed electrical failures. 3D design implementation will continue to grow in 2012 with the majority employing a silicon interposer, and the EDA tools needed for both interposer and full 3D designs are largely in place. Logic BIST and hybrid BIST/compression techniques will start to play an increasingly important role in IC manufacturing test as smaller feature sizes, increased gate counts, and 3D designs create more demand to improve test quality and control test cost.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Today, I wrap up this mini-series by presenting the predictions in the areas of IP and physical design.
IP
Bill Neifert Chief Technology Officer Carbon Design Systems
Time to market pressures will force more IP sales to instead become subsystems sales
This is a trend we’ve seen with design teams over the past year or so which is gaining more and more momentum. The increasing complexity of individual IP blocks means that when multiple blocks are integrated together it’s more and more difficult to tie them all together well in an optimal configuration, especially where software is involved. It makes much more sense to buy the entire, configured subsystem from a single vendor and just make minor configuration tweaks to the provided hardware and software.
Ed Bard, Sr. Director of Marketing, Digital IP, Memories, Logic Libraries, FPGA Prototyping & Synthesis at Synopsys.
Complete, pre-validated subsystems will hit the IP market as the next evolution in the IP business. Unlike the traditional view of SoC IP, which is hardware centric and delivered as RTL or GDSII, subsystems consist of pre-integrated hardware, software and prototypes that are SoC-ready, meaning designers can just drop it in and go. As more functionality gets integrated into today’s designs, having multiple, integrated IP blocks that are verified and optimized for a specific function will enable designers to significantly reduce integration effort. In the end, what differentiates the IP subsystem will be the software and prototyping capabilities, allowing engineers to accelerate their development cycle by addressing their challenges at a system-level, rather than the block-level.
Physical Issues
Paul van Besouw President and CEO Oasys Design Systems
A big issue for 2012 will be noise. Signal voltages are now down close to the noise voltages, which often don't scale with the power supply at all. We are also getting closer to having to worry about counting atoms. After all, a 20nm gate is 200 hydrogen atoms across, or about 80 copper atoms, never mind how few atoms make up a gate oxide. Creating and analyzing physical design must be done at as high a level as possible, ideally at the chip level.
Paul van Besouw President and CEO Oasys Design Systems
At 65nm, the big issue facing designers was whether Joe Costello could be lured back into EDA if he was allowed to dress as a rock star. By 45nm, Apple had decided to move into IC design and make its own semiconductors, so the big question was whether Mac was superior to PC. At 32nm lithography issues dominated and the big question was whether it was possible to surf 193nm light waves to working silicon, going big and really small at the same time. For 2012 and for 28-22nm design, the big question remains to be defined but for sure will be on video in June. Editor note: hmmm, now what could that imply?
Mentor Design to Silicon group
IBS Inc. states that 28nm designs starts will increase by 50% over 2011, while current 28nm designs will be ramping to full production. We project this will cause fabless companies to seek second sources foundries to satisfy demand, driving additional 28nm design efforts. We expect increases in the number of 20nm test chips in 2012, with the first full reticle design tape outs in 2013. At 20nm, foundries will introduce cell-based “smart fill” techniques to reduce file size and DRC run times. Double patterning for 20nm will require more extraction corners, creating demand for faster, multi-CPU extraction tools. Thinner gate oxides and multi-voltage designs will require more rigorous circuit checking to avoid delayed electrical failures. 3D design implementation will continue to grow in 2012 with the majority employing a silicon interposer, and the EDA tools needed for both interposer and full 3D designs are largely in place. Logic BIST and hybrid BIST/compression techniques will start to play an increasingly important role in IC manufacturing test as smaller feature sizes, increased gate counts, and 3D designs create more demand to improve test quality and control test cost.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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