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Webinar: Power Issues for Chip and Board
Brian Bailey
1/23/2012 5:36 PM EST
Last week, I had the pleasure to record the first part of a webinar that will go live on January 31st. This webinar talks about power and power integrity and the two speakers, Arvind Shanmugavel, the director of applications engineering for Apache Design (a subsidiary of Ansys) and Randy White, the technical marketing manager for measurement solutions focused on embedded systems at Tektronix, had some amazing insights into this broad and complex subject. When the webinar is broadcast, you will have to opportunity to ask these speakers question which will be answered live. This is one webinar that you really do not want to miss! Register today and enjoy next week.
Abstract:
Power used to be a secondary concern when it comes to chip or system design, but with the rapid rise in importance of mobile devices, increasing chip densities, and a rise in the levels of concurrency, power consumption, power dissipation, heat dissipation, and power integrity and becoming major primary design considerations at all stages in the design flow. Many chip design techniques are making this problem more difficult, such as multiple power domains and clock gating, while high speed interfaces are creating problems with board layouts and 3D packaging techniques are raising many kinds of new challenges. Power management is an important topic for every design company to remain competitive, to increase yields and to deal with the longevity issues required for emerging industries such as automotive.
Details:
January 31st 10:00 am Pacific 1pm Eastern
Register:
Click here to register
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Abstract:
Power used to be a secondary concern when it comes to chip or system design, but with the rapid rise in importance of mobile devices, increasing chip densities, and a rise in the levels of concurrency, power consumption, power dissipation, heat dissipation, and power integrity and becoming major primary design considerations at all stages in the design flow. Many chip design techniques are making this problem more difficult, such as multiple power domains and clock gating, while high speed interfaces are creating problems with board layouts and 3D packaging techniques are raising many kinds of new challenges. Power management is an important topic for every design company to remain competitive, to increase yields and to deal with the longevity issues required for emerging industries such as automotive.
Details:
January 31st 10:00 am Pacific 1pm Eastern
Register:
Click here to register
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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