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Upcoming Conferences: calls and more – Feb 3rd
Brian Bailey
2/3/2012 12:40 PM EST
If you have an upcoming conference related to EDA tools, techniques, IP or design practices and would like me to include your call for papers, contribution or participation in this conference roundup, then please send me an email.
In this issue:
Call for Papers
14th IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2012)
4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms
3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
The 21th International Workshop on Logic & Synthesis
International Conference on Field Programmable Logic and Applications FPL 2012
Conference Participation
DATE 2012 Announces Growing Exhibition and Availability of Advanced Program
Call for Papers
14th IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2012)
Moscone Center, San Francisco, California. June 3, 2012
Co-located with the 49th IEEE/ACM Design Automation Conference
Co-sponsored by ACM SIGDA and the IEEE Computer Society
http://www.sliponline.org
The 14th International Workshop of System Level Interconnect Prediction (SLIP) will be co-located with the 49th IEEE/EDAC/ACM Design Automation Conference on June 3, 2012 at the Moscone Center, San Francisco, California. The general technical scope of the workshop is the design, analysis and prediction of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, and special sessions. Regular papers will be double blind reviewed. Submissions with author information will be rejected. We accept papers based on novelty and contributions. The accepted papers will be published in the proceedings of SLIP 2012, which will also be included in the ACM Digital Library. Note that ACM will hold the copyright for SLIP 2012 proceedings. Authors of accepted papers must sign an ACM copyright release form for their papers.
Representative technical topics include, but are not limited to:
1. Interconnect prediction and optimization at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects
7. High speed chip-to-chip interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. 3D interconnect design and prediction, including TSV architecture and monolithic 3D stacking
11. Emerging interconnect technologies, e.g., RF interconnects, photonic networks, carbon-based interconnects, etc.
12. Synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, etc.
Important dates:
Abstract Registration Due: Feb. 27, 2012
Submission Deadline: Mar. 5, 2012
Notification Due: Apr. 6, 2012
Final Version Due: Apr. 23, 2012
The 4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2 2012)
http://www.arcos.inf.uc3m.es/ispa12/workshops.shtml
In conjunction with
The 10th IEEE International Symposium on Parallel and Distributed Processing with Applications http://www.arcos.inf.uc3m.es/ispa2012/
Madrid, Spain July 10-13, 2012
Scope:
Multicore systems are dominating the processor market ranging from embedded to high-performance systems. Early multicore processors just included two or four cores; currently some processors integrate more than ten cores and, as the node shrinks in future technology generations, it is expected that the number of cores will continue increasing in future manufactured systems.
To take advantage of the high number of cores efficient load balancing and scheduling policies or strategies are required. In addition, it remains a challenge to identify and productively program applications for these systems with a resulting substantial performance improvement. On the other hand, the system designer must trade off performance versus power consumption, which is a major concern in current microprocessors. Therefore current design must focus on new architectures or architectural mechanisms addressing this trade off. Finally, most real-time embedded applications are requiring high-performance computing and multicore and multithreaded processors are becoming the typical design choice. The aim of this workshop is to provide a forum for engineers and scientists to address the resulting challenge and to present new ideas, applications, and experience on all aspects of multicore and multithreaded systems. Authors are invited to submit high quality papers representin g their original work in (but not limited to) the following topics targeting multicore multithreaded processors:
* Multicore and multithreaded architectures
* Power-aware multicore architectures and computing
* Embedded multicore real-time systems
* Scheduling and load balancing
* Multicore programming
* Parallel and distributed algorithms
Paper Submission and Publication:
Submit original unpublished papers in PDF formats at the ISPA-2012 submission system: https://www.easychair.org/account/signin.cgi?conf=ispa2012, please select Track " Multicore and Multithreaded Architectures and Algorithms-M2A2". All submitted manuscripts will be reviewed at least by three expert reviewers. Submissions will be judged on originality, technical strength, quality of presentation, and relevance to the workshop scope.
All accepted papers will be included in the ISPA-2012 proceedings published by IEEE Computer Society. The length of the camera-ready manuscripts will be limited to 8 pages in IEEE CS proceedings paper format. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers will not be published.
Distinguished papers accepted and presented in M2A2 2012, after further revisions, could be considered for publication in special issues of SCI indexed international journals.
Important Dates:
February 28, 2012: Paper Submission Due
March 15, 2012: Notification of Acceptance/Rejection April 15, 2012: Camera-Ready Due July 10-13, 2012: Workshop Takes Place
The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies HEART2012
Okinawa, Japan May 30 - June 1, 2012 <http://www.isheart.org>
IMPORTANT DATES (UTC):
- Paper submission: February 21, 2012
- Author notification: March 26, 2012
- Design contest entry: March 26, 2012
- Camera-ready due: April 12, 2012
- Design contest: May 30, 2012
- Workshop date: May 31 - June 1, 2012
The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:
* Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA,
GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core architectures, NoC
architectures, 3D-stacking technologies and optical devices
* Software and applications:
- Novel applications for efficient acceleration systems/platforms,
and custom computing
- Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.
We will accept regular and short papers for oral and poster presentation, respectively. All the accepted regular papers will be published in the post-proceedings that will be published as a special issue of ACM SIGARCH Computer Architecture News (CAN) and will also be available in ACM Digital Library. By submitting your work to the HEART2012 workshop, you grant permission for ACM to publish the material in print and digital formats in ACM's Computer Architecture News and the ACM archive. The short papers will be included in the workshop handout distributed at the workshop. One of the authors must attend the workshop and present their work as a condition of publication.
All papers must be no more than 6 pages (two columns, US letter size, 10 points for main body text) in length and prepared in PDF format. For double-blind review, manuscripts must NOT identify authors; names of authors, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. Full formatting and submission instructions are available at the HEART2012 web-site.
For more information, please visit <http://www.isheart.org/>.
The 21th International Workshop on Logic & Synthesis
University of California, Berkeley June 1 - 3, 2012
Co-located with the Design Automation Conference website: http://www.iwls.org
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The emphasis is on novelty and intellectual rigor. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions.
Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.
Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. Only original and previously unpublished material is permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.
Abstract submission: March 9, 2012
Submission deadline for papers: March 16, 2012 - 11.59pm HAST
Notification of acceptance: April 2, 2012
Final version due: May 5, 2012
*** The submission deadline of March 16, 2012 is final
International Conference on Field Programmable Logic and Applications FPL 2012
Oslo, Norway, August 29-31, 2012 http://www.fpl.org
Call for papers (pdf):http://www.fpl2012.org/FPL2012_CFP.pdf
Submission Deadline: March 20, 2012
Acceptance Notification: June 1, 2012
Authors of selected papers will be invited to submit extended versions to a special issue in IET Computers& Digital Techniques. For its 22nd issue, FPL will also continue to have awards for outstanding achievements and contributions.
(FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 21 years, many of the advances achieved in reconfigurable architectures, applications, design methods and tools have been first published in the proceedings of the FPL conference series.
Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to:
applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.
FPL is organized yearly in Europe and attended by top-level scientists and researchers. The 22th FPL continues the tradition of the previous editions and will be hosted by the University of Oslo, Norway from August 29-31, 2012.
Confirmed keynotes: Prof. Michael J. Flynn, em. Professor Stanford University/chairman of Maxeler Technologies. Dr. Steve Teig, President and CTO of Tabula, Dr. Steve Trimberger, Xilinx Fellow and Dr. Stan Williams, HP Senior Fellow.
Conference Participation
DATE 2012 Announces Growing Exhibition and Availability of Advanced Program
The full technical program for DATE 2012, the major global event in Europe which will again push innovation in the worldwide electronics industry, is now available at:
www.date-conference.com
The DATE 2012 program is clearly focused on industrial and academic needs. It consists of 56 technical sessions and around 200 papers, plus an executive track featuring 3 sessions with industry-leading executives. The program is completed by Tutorials given by world market-leaders and key scientists.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
In this issue:
Call for Papers
14th IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2012)
4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms
3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
The 21th International Workshop on Logic & Synthesis
International Conference on Field Programmable Logic and Applications FPL 2012
Conference Participation
DATE 2012 Announces Growing Exhibition and Availability of Advanced Program
Call for Papers
14th IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2012)
Moscone Center, San Francisco, California. June 3, 2012
Co-located with the 49th IEEE/ACM Design Automation Conference
Co-sponsored by ACM SIGDA and the IEEE Computer Society
http://www.sliponline.org
The 14th International Workshop of System Level Interconnect Prediction (SLIP) will be co-located with the 49th IEEE/EDAC/ACM Design Automation Conference on June 3, 2012 at the Moscone Center, San Francisco, California. The general technical scope of the workshop is the design, analysis and prediction of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, and special sessions. Regular papers will be double blind reviewed. Submissions with author information will be rejected. We accept papers based on novelty and contributions. The accepted papers will be published in the proceedings of SLIP 2012, which will also be included in the ACM Digital Library. Note that ACM will hold the copyright for SLIP 2012 proceedings. Authors of accepted papers must sign an ACM copyright release form for their papers.
Representative technical topics include, but are not limited to:
1. Interconnect prediction and optimization at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects
7. High speed chip-to-chip interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. 3D interconnect design and prediction, including TSV architecture and monolithic 3D stacking
11. Emerging interconnect technologies, e.g., RF interconnects, photonic networks, carbon-based interconnects, etc.
12. Synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, etc.
Important dates:
Abstract Registration Due: Feb. 27, 2012
Submission Deadline: Mar. 5, 2012
Notification Due: Apr. 6, 2012
Final Version Due: Apr. 23, 2012
The 4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2 2012)
http://www.arcos.inf.uc3m.es/ispa12/workshops.shtml
In conjunction with
The 10th IEEE International Symposium on Parallel and Distributed Processing with Applications http://www.arcos.inf.uc3m.es/ispa2012/
Madrid, Spain July 10-13, 2012
Scope:
Multicore systems are dominating the processor market ranging from embedded to high-performance systems. Early multicore processors just included two or four cores; currently some processors integrate more than ten cores and, as the node shrinks in future technology generations, it is expected that the number of cores will continue increasing in future manufactured systems.
To take advantage of the high number of cores efficient load balancing and scheduling policies or strategies are required. In addition, it remains a challenge to identify and productively program applications for these systems with a resulting substantial performance improvement. On the other hand, the system designer must trade off performance versus power consumption, which is a major concern in current microprocessors. Therefore current design must focus on new architectures or architectural mechanisms addressing this trade off. Finally, most real-time embedded applications are requiring high-performance computing and multicore and multithreaded processors are becoming the typical design choice. The aim of this workshop is to provide a forum for engineers and scientists to address the resulting challenge and to present new ideas, applications, and experience on all aspects of multicore and multithreaded systems. Authors are invited to submit high quality papers representin g their original work in (but not limited to) the following topics targeting multicore multithreaded processors:
* Multicore and multithreaded architectures
* Power-aware multicore architectures and computing
* Embedded multicore real-time systems
* Scheduling and load balancing
* Multicore programming
* Parallel and distributed algorithms
Paper Submission and Publication:
Submit original unpublished papers in PDF formats at the ISPA-2012 submission system: https://www.easychair.org/account/signin.cgi?conf=ispa2012, please select Track " Multicore and Multithreaded Architectures and Algorithms-M2A2". All submitted manuscripts will be reviewed at least by three expert reviewers. Submissions will be judged on originality, technical strength, quality of presentation, and relevance to the workshop scope.
All accepted papers will be included in the ISPA-2012 proceedings published by IEEE Computer Society. The length of the camera-ready manuscripts will be limited to 8 pages in IEEE CS proceedings paper format. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers will not be published.
Distinguished papers accepted and presented in M2A2 2012, after further revisions, could be considered for publication in special issues of SCI indexed international journals.
Important Dates:
February 28, 2012: Paper Submission Due
March 15, 2012: Notification of Acceptance/Rejection April 15, 2012: Camera-Ready Due July 10-13, 2012: Workshop Takes Place
The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies HEART2012
Okinawa, Japan May 30 - June 1, 2012 <http://www.isheart.org>
IMPORTANT DATES (UTC):
- Paper submission: February 21, 2012
- Author notification: March 26, 2012
- Design contest entry: March 26, 2012
- Camera-ready due: April 12, 2012
- Design contest: May 30, 2012
- Workshop date: May 31 - June 1, 2012
The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:
* Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA,
GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core architectures, NoC
architectures, 3D-stacking technologies and optical devices
* Software and applications:
- Novel applications for efficient acceleration systems/platforms,
and custom computing
- Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.
We will accept regular and short papers for oral and poster presentation, respectively. All the accepted regular papers will be published in the post-proceedings that will be published as a special issue of ACM SIGARCH Computer Architecture News (CAN) and will also be available in ACM Digital Library. By submitting your work to the HEART2012 workshop, you grant permission for ACM to publish the material in print and digital formats in ACM's Computer Architecture News and the ACM archive. The short papers will be included in the workshop handout distributed at the workshop. One of the authors must attend the workshop and present their work as a condition of publication.
All papers must be no more than 6 pages (two columns, US letter size, 10 points for main body text) in length and prepared in PDF format. For double-blind review, manuscripts must NOT identify authors; names of authors, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. Full formatting and submission instructions are available at the HEART2012 web-site.
For more information, please visit <http://www.isheart.org/>.
The 21th International Workshop on Logic & Synthesis
University of California, Berkeley June 1 - 3, 2012
Co-located with the Design Automation Conference website: http://www.iwls.org
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The emphasis is on novelty and intellectual rigor. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions.
Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.
Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. Only original and previously unpublished material is permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.
Abstract submission: March 9, 2012
Submission deadline for papers: March 16, 2012 - 11.59pm HAST
Notification of acceptance: April 2, 2012
Final version due: May 5, 2012
*** The submission deadline of March 16, 2012 is final
International Conference on Field Programmable Logic and Applications FPL 2012
Oslo, Norway, August 29-31, 2012 http://www.fpl.org
Call for papers (pdf):http://www.fpl2012.org/FPL2012_CFP.pdf
Submission Deadline: March 20, 2012
Acceptance Notification: June 1, 2012
Authors of selected papers will be invited to submit extended versions to a special issue in IET Computers& Digital Techniques. For its 22nd issue, FPL will also continue to have awards for outstanding achievements and contributions.
(FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 21 years, many of the advances achieved in reconfigurable architectures, applications, design methods and tools have been first published in the proceedings of the FPL conference series.
Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to:
applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.
FPL is organized yearly in Europe and attended by top-level scientists and researchers. The 22th FPL continues the tradition of the previous editions and will be hosted by the University of Oslo, Norway from August 29-31, 2012.
Confirmed keynotes: Prof. Michael J. Flynn, em. Professor Stanford University/chairman of Maxeler Technologies. Dr. Steve Teig, President and CTO of Tabula, Dr. Steve Trimberger, Xilinx Fellow and Dr. Stan Williams, HP Senior Fellow.
Conference Participation
DATE 2012 Announces Growing Exhibition and Availability of Advanced Program
The full technical program for DATE 2012, the major global event in Europe which will again push innovation in the worldwide electronics industry, is now available at:
www.date-conference.com
The DATE 2012 program is clearly focused on industrial and academic needs. It consists of 56 technical sessions and around 200 papers, plus an executive track featuring 3 sessions with industry-leading executives. The program is completed by Tutorials given by world market-leaders and key scientists.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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