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Upcoming Conferences: calls and more – Feb 9th
Brian Bailey
2/9/2012 10:32 AM EST
If you have an upcoming conference related to EDA tools, techniques, IP or design practices and would like me to include your call for papers, contribution or participation in this conference roundup, then please send me an email.
In this issue:
Call for Papers
VLSI Design Journal: Special Issue on New Algorithmic Techniques for EDA Problems
Embedded Systems Week. Tampere, Finland, October 7-12, 2012
International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
TODAES Special Section on Adaptive Power Management for Energy and Temperature Aware Computing Systems
Forum on specification & Design Languages FDL2012
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Electronic System Level Synthesis Conference
Conference Participation
The 8th International Symposium on Applied Reconfigurable Computing
Call for Papers
VLSI Design Journal: Special Issue on New Algorithmic Techniques for EDA Problems
http://www.hindawi.com/journals/vlsi/si/eda/ for details.
Original papers are invited for a special issue of the VLSI Design journal on "New Algorithmic Techniques in EDA". There are two broad sets of effects that result from the rapidly decreasing feature sizes in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant increase in the number and the diversity of systems that are implemented on a single chip (b) Further exacerbation of old problems and the introduction of new ones such as electrical/physical effects like power dissipation and leakage/temperature issues at all levels, lithography and manufacturing problems leading to appreciable variability, and reliability of the design stemming from reduced feature sizes, to name a few. These issues present significant challenges to the entire range of EDA tools from ESL (e.g., memory synthesis and hierarchy design, effective power analysis and optimization) to gate-level synthesis (e.g., detailed power optimization across millions of gates under timing yield and voltage-island constraints). EDA software has thus become immensely complex, and algorithmic innovations are needed to tackle these new problems with efficiency and efficacy at various stages of the VLSI design flow (e.g., ESL including high-level synthesis, logic/physical synthesis, physical extraction and timing models, variability/manufacturing aware optimization, simulation and analysis, and verification).
We are thus asking for original paper submissions addressing critical problems in EDA using effective algorithmic techniques that are either new or uncommon in EDA. More formally put, the desired algorithmic techniques are those that either (a) are completely new in their usage in the EDA domain, or (b) have been proposed only over the last five years or so or (c) have been proposed more than five years back, but have been used sparsely in EDA. The proposed algorithms should empirically demonstrate efficacy in solving the targeted EDA problems. When submitting your paper to this special issue, please include a new section titled "New Algorithmic Technique(s) Used" that immediately follows the "Introduction" section, for an explicit identification of the algorithmic technique(s) used, and a justification, possibly with citations, that they fit into one of the above categories (a-c). Also, as with any other journal publication, if the submission is an extension to a conference paper, please also include a paragraph of justification in the "Introduction" section (at least 30% new material is required).
SUBMISSIONS
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/
Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/
Manuscript Due (EXTENDED DEADLINE): Friday, 16 March 2012 First Round of Reviews: Friday, 15 June 2012 Publication Date Friday: 10 August 2012
Embedded Systems Week.
Tampere, Finland, October 7-12, 2012
www.esweek.org
++ CASES +++ CODES+ISSS +++ EMSOFT +++ Workshops +++ Tutorials ++
ESWeek 2012 will be co-located with SoC 2012
About ESWeek
ESWeek is a premier event covering all aspects of embedded systems and software. It brings together conferences, tutorials, and workshops centered on various aspects of embedded systems research and development. Three leading conferences in the area - CASES, CODES+ISSS, and EMSOFT - will take place at the same time and location, allowing attendees to benefit from a wide range of topics covered by these conferences and their associated tutorials and workshops.
Dates
- Abstract submission: March 28, 2012
- Full paper submission: April 04, 2012
- Acceptance notification: July 03, 2012
- Camera ready version: July 31, 2012
- Conference: October 7-12, 2012
For paper submission instructions see: www.esweek.org
International Journal of Embedded and Real-Time Communication Systems
The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers
The International Journal of Embedded and Real-Time Communication Systems (IJERTCS) extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following:
Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques
Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs
All inquiries and submissions should be sent to:
Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi
TODAES Special Section on Adaptive Power Management for Energy and Temperature Aware Computing Systems
In order to keep a sustained growth of modern IT technology, it is important to curb the energy usage and carbon emission. Particular effort is needed to control the power and energy consumption of IT facilities and its cooling systems. Besides the environmental impact, excessive power consumption also reduces system reliability, increases cooling cost and cuts the battery cycle time. Effective power and thermal management will help to relieve the power and temperature bottleneck of today’s VLSI design and accelerate the growth of the information technology industries. It will also enable today’s computing and communication device to work efficiently with emerging energy storage and energy harvesting technologies to achieve energy autonomy.
A robust power management system should be able to work on different types of hardware with variable workload. The ability to adapt to the environment is the key to maintain its efficiency. This journal special section will cover recent progress on adaptive power management, including runtime monitoring, modeling, classification, learning and controlling techniques for power and temperature optimization of a computing device. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design and implementation of adaptive power management.
1. Novel power (temperature) management techniques based on control theory or machine learning algorithms
2. Runtime system monitoring, workload classification and power modeling techniques
3. Runtime power management with the consideration of energy storage and energy harvesting technologies
4. The impact of power (temperature) management on system reliability and information security
5. Experiences, case studies, and lessons learned for adaptive power management applications
The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25. Please clearly state (as a note to the editor-in-chief when submitting the paper via ManuscriptOne and on the first page of the submission under the
abstract) that the paper is submitted for consideration under the "Adaptive Power Management for Energy and Temperature Aware Computing Systems" special issue.
Forum on specification & Design Languages FDL2012
Vienna, AustriaSeptember 18-20, 2012
FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods and tools for the design of electronic systems. The Forum is organized around four Thematic Areas (TA) described below and includes working sessions, poster sessions, embedded tutorials, panels and technical discussions. Industrial Workshops and Fringe Meetings such as user group or standardization meetings are also held in conjunction with the Forum.
Technical Areas
Assertion Based Design, Verification & Debug
Language-Based System Design
Embedded Analog and Mixed-Signal System Design
UML and MDE for Embedded System Specification & Design
Requirements for Submission
REGULAR AND SHORT PAPERS:
Regular papers provide comprehensive details on innovative and complete research or applicative work with evidence of experimental results. Regular papers may also include proposals for standardization. Authors are encouraged to outline work in progress, industrial case studies, or user experiences as short papers. Accepted short papers will be presented as posters in dedicated sessions, allowing to present advances achieved since submission. Submitted papers should be anonymous, are required to describe original unpublished work and must not be under consideration for publication elsewhere.
PUBLICATIONS:
After the conference, papers and presentations will be published on the ECSI website together with the keynote presentations (subject to confidentiality issues) and tutorial documents. In addition, the accepted and presented papers will be published in IEEE Xplore. The authors of the best regular papers may be invited to prepare an extended manuscript for journal publication.
EMBEDDED TUTORIALS:
Proposals for half-day (4 hours) embedded tutorials on specific topics around any of the four workshops will be accepted depending on topic relevance and evidence of a comprehensive agenda. A one page description of the tutorial including title, presenters, contents, and the relevant track(s) should be sent to fdl2012@ecsi.org. A maximum of three tutorial authors is recommended. Accepted tutorials will get one free registration to the Forum per tutorial.
PANELS, SPECIAL SESSIONS, WORKING GROUPS, PROJECT MEETINGS, DEMONSTRATIONS:
Proposal for special sessions (panels, working sessions, standardization or user group meetings, etc.) around any of the four TA tracks are invited and will be accepted depending on their relevance and interest to the audience. They will be embedded in regular workshops. A one page description including title, participants, contents, and the relevant track(s) should be sent to fdl2012@ecsi.org. Companies, universities or other organizations wishing to demonstrate innovative tools and environments for the topics described above should send proposals to fdl2012@ecsi.org.
Important Dates
Paper submission deadline: 02 April 2012
Special session & embedded tutorial proposal deadline: 09 April 2012
Notification of acceptance: 30 May 2012
Final versions of accepted papers & presenters' registration: 30 July 2012
Proposals for on-site meetings: 30 August 2012
FDL 2012: 18-20 Sept 2012
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Beijing, China June 16, 2012
Co-located with PLDI 2012,
http://safari.ece.cmu.edu/MSPC2012/
Abstract deadline: March 5, 2012 (11:59pm EST)
Paper deadline: March 12, 2012 (11:59pm EDT)
Notification: April 23, 2012
Final submission: May 1, 2012
Memory continues to be a major bottleneck in almost all computing systems. It is becoming more so as more cores and agents are sharing parts of the memory system and as applications that run on the cores are becoming increasingly data intensive. Continuing the tradition of six previous successful incarnations, MSPC 2012 will provide a forum for publishing and discussing all aspects of memory performance and correctness on a variety of systems (multi-core, desktop, embedded, server/cloud, high-performance computing, sensor, etc) and related software and hardware innovations at various levels of the technology stack. We invite new submissions that tackle issues in memory system performance, efficiency, correctness, and dependability in both hardware and software layers. Example areas of interest include but are not limited to the following:
Software, hardware, and hybrid approaches are encouraged. In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.
Submission Guidelines: We encourage the submission of not-fully-polished but provocative short papers (6--8 pages; 8 pages maximum) or position abstracts
(1--2 pages; 2 pages maximum). Paper submissions should use standard ACM SIGPLAN conference format (10pt). Copies of accepted papers will be made available at the workshop and published in the ACM digital library. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work.
Electronic System Level Synthesis Conference
San Francisco, California, USA June 2-3, 2012 www.ecsi.org/eslsyn
Workshop Description
The ever-increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementations are needed for designing both HW and SW parts. ESL design does not only provide system architects with the right tools to make the right decisions about the system architecture, it includes the methodologies and techniques that correlate the ESL model. A well-connected ESL-to-implementation design flow is needed.
The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cycle time all together, breaking the trend to compromise on the evaluation of various design implementation options. Designing at higher levels of abstraction is a viable way to better cope with the system design complexity, to verify earlier in the design process and to increase code reuse.
The Electronic System Level Synthesis Conference ESLsyn focuses on automated system design methods that enable efficient modelling of systems to provide the capability to synthesize HW platforms and embedded software with particular aspects related to synthesis.
Topics
ESLsyn will focus on the five key tasks related to the design and verification of complex, programmable electronic products:
- The development of product architectures and specifications, including the incorporation and configuration of IP
- The mapping of applications to a product specification, including hardware/software partitioning and processor optimization
- The creation of pre-silicon, virtual hardware platforms for software development
- The determination/automation of a hardware implementation for that architecture
- The development of reference models for verifying the hardware
Furthermore, ESLsyn addresses:
- Cyber-Physical System/System/Platform related to ESL design flow
- High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis for HW Design in cooperation with the ESL design flow
- Embedded Software Synthesis that is used into the ESL design flow
The above list is not an exhaustive list of topics addressed by ESLsyn ; contributions related to ESLsyn problems in general not listed here are highly welcome. Submissions may be theoretical scientific papers, research in progress, case studies, tool use cases and best practice, as well as industry experiences.
Important Information for Authors
Authors must follow the paper submission guidelines. Details can be found at http://www.ecsi.org/eslsyn . Questions, contact office@ecsi.org.
Important Dates
Paper Submission Deadline: March 23, 2012
Notification of Acceptance: May 14, 2012
Full Final Paper Submission: May 14, 2012
Copyright Forms: May 14, 2012
Author Registration: May 26, 2012
Presentations Submission + Presenter Bio May 26, 2012
Conference Participation
The 8th International Symposium on Applied Reconfigurable Computing
19-23 March 2012, Hong Kong
Web: http://arc2012.hk
Hosted by the Chinese University of Hong Kong and City University Hong Kong
Registration is now open for ARC 2012, with discounted early registration rates until 19th February:
http://arc2012.hk/registration.html
We have an exciting line-up of plenary speakers including:
Prof. Michael J. Flynn, Stanford University Prof. Dr.-Ing. Sorin A. Huss, Technische Universitaet Darmstadt, Germany Prof. Cetin Kaya Koc, University of California Santa Barbara Prof. Wayne Luk, Imperial College London Grant Martin, Chief Scientist, Tensilica Inc
The preliminary program is now available at:
http://arc2012.hk/preliminary.html
http://arc2012.hk/program.html
Two leading Reconfigurable Technology companies: Xilinx & Altera will also offer Industrial workshops at ARC:
http://arc2012.hk/tutorial.html
We would like to acknowledge the generous support from our sponors:
http://arc2012.hk/sponsor.html
The ARC2012 Symposium
Reconfigurable Computing technologies offer the promise of substantial gains in performance and power efficiency over traditional architectures via customising, even at runtime, the topology of the underlying architecture to match the specific needs of a given application.
Contemporary configurable architectures allow for the definition of specific functional and storage units, adapted to the functions, bit-widths and control structures of a given computation. This flexibility enabled by reconfiguration can also be seen as a basic technique for overcoming permanent and transient failures on emerging device structures.
ARC aims at bringing together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this promising technology. This year's symposium will also host a series of international invited speakers to share their insights into the future of reconfigurable technology.
The ARC 2012 proceedings will appear in the Springer Lecture Notes in Computer Science (LNCS) series and also be available in the SpringerLink on-line service. Additionally, the top papers will be invited to submit to a special section of a forthcoming journal issue of Elsevier Microprocessors and Microsystems (MICPRO).
Brian Bailey – keeping you covered
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In this issue:
Call for Papers
VLSI Design Journal: Special Issue on New Algorithmic Techniques for EDA Problems
Embedded Systems Week. Tampere, Finland, October 7-12, 2012
International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
TODAES Special Section on Adaptive Power Management for Energy and Temperature Aware Computing Systems
Forum on specification & Design Languages FDL2012
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Electronic System Level Synthesis Conference
Conference Participation
The 8th International Symposium on Applied Reconfigurable Computing
Call for Papers
VLSI Design Journal: Special Issue on New Algorithmic Techniques for EDA Problems
http://www.hindawi.com/journals/vlsi/si/eda/ for details.
Original papers are invited for a special issue of the VLSI Design journal on "New Algorithmic Techniques in EDA". There are two broad sets of effects that result from the rapidly decreasing feature sizes in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant increase in the number and the diversity of systems that are implemented on a single chip (b) Further exacerbation of old problems and the introduction of new ones such as electrical/physical effects like power dissipation and leakage/temperature issues at all levels, lithography and manufacturing problems leading to appreciable variability, and reliability of the design stemming from reduced feature sizes, to name a few. These issues present significant challenges to the entire range of EDA tools from ESL (e.g., memory synthesis and hierarchy design, effective power analysis and optimization) to gate-level synthesis (e.g., detailed power optimization across millions of gates under timing yield and voltage-island constraints). EDA software has thus become immensely complex, and algorithmic innovations are needed to tackle these new problems with efficiency and efficacy at various stages of the VLSI design flow (e.g., ESL including high-level synthesis, logic/physical synthesis, physical extraction and timing models, variability/manufacturing aware optimization, simulation and analysis, and verification).
We are thus asking for original paper submissions addressing critical problems in EDA using effective algorithmic techniques that are either new or uncommon in EDA. More formally put, the desired algorithmic techniques are those that either (a) are completely new in their usage in the EDA domain, or (b) have been proposed only over the last five years or so or (c) have been proposed more than five years back, but have been used sparsely in EDA. The proposed algorithms should empirically demonstrate efficacy in solving the targeted EDA problems. When submitting your paper to this special issue, please include a new section titled "New Algorithmic Technique(s) Used" that immediately follows the "Introduction" section, for an explicit identification of the algorithmic technique(s) used, and a justification, possibly with citations, that they fit into one of the above categories (a-c). Also, as with any other journal publication, if the submission is an extension to a conference paper, please also include a paragraph of justification in the "Introduction" section (at least 30% new material is required).
SUBMISSIONS
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/
Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/
Manuscript Due (EXTENDED DEADLINE): Friday, 16 March 2012 First Round of Reviews: Friday, 15 June 2012 Publication Date Friday: 10 August 2012
Embedded Systems Week.
Tampere, Finland, October 7-12, 2012
www.esweek.org
++ CASES +++ CODES+ISSS +++ EMSOFT +++ Workshops +++ Tutorials ++
ESWeek 2012 will be co-located with SoC 2012
About ESWeek
ESWeek is a premier event covering all aspects of embedded systems and software. It brings together conferences, tutorials, and workshops centered on various aspects of embedded systems research and development. Three leading conferences in the area - CASES, CODES+ISSS, and EMSOFT - will take place at the same time and location, allowing attendees to benefit from a wide range of topics covered by these conferences and their associated tutorials and workshops.
Dates
- Abstract submission: March 28, 2012
- Full paper submission: April 04, 2012
- Acceptance notification: July 03, 2012
- Camera ready version: July 31, 2012
- Conference: October 7-12, 2012
For paper submission instructions see: www.esweek.org
International Journal of Embedded and Real-Time Communication Systems
The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers
The International Journal of Embedded and Real-Time Communication Systems (IJERTCS) extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following:
Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques
Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs
All inquiries and submissions should be sent to:
Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi
TODAES Special Section on Adaptive Power Management for Energy and Temperature Aware Computing Systems
In order to keep a sustained growth of modern IT technology, it is important to curb the energy usage and carbon emission. Particular effort is needed to control the power and energy consumption of IT facilities and its cooling systems. Besides the environmental impact, excessive power consumption also reduces system reliability, increases cooling cost and cuts the battery cycle time. Effective power and thermal management will help to relieve the power and temperature bottleneck of today’s VLSI design and accelerate the growth of the information technology industries. It will also enable today’s computing and communication device to work efficiently with emerging energy storage and energy harvesting technologies to achieve energy autonomy.
A robust power management system should be able to work on different types of hardware with variable workload. The ability to adapt to the environment is the key to maintain its efficiency. This journal special section will cover recent progress on adaptive power management, including runtime monitoring, modeling, classification, learning and controlling techniques for power and temperature optimization of a computing device. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design and implementation of adaptive power management.
1. Novel power (temperature) management techniques based on control theory or machine learning algorithms
2. Runtime system monitoring, workload classification and power modeling techniques
3. Runtime power management with the consideration of energy storage and energy harvesting technologies
4. The impact of power (temperature) management on system reliability and information security
5. Experiences, case studies, and lessons learned for adaptive power management applications
The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25. Please clearly state (as a note to the editor-in-chief when submitting the paper via ManuscriptOne and on the first page of the submission under the
abstract) that the paper is submitted for consideration under the "Adaptive Power Management for Energy and Temperature Aware Computing Systems" special issue.
Forum on specification & Design Languages FDL2012
Vienna, AustriaSeptember 18-20, 2012
FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods and tools for the design of electronic systems. The Forum is organized around four Thematic Areas (TA) described below and includes working sessions, poster sessions, embedded tutorials, panels and technical discussions. Industrial Workshops and Fringe Meetings such as user group or standardization meetings are also held in conjunction with the Forum.
Technical Areas
Assertion Based Design, Verification & Debug
Language-Based System Design
Embedded Analog and Mixed-Signal System Design
UML and MDE for Embedded System Specification & Design
Requirements for Submission
REGULAR AND SHORT PAPERS:
Regular papers provide comprehensive details on innovative and complete research or applicative work with evidence of experimental results. Regular papers may also include proposals for standardization. Authors are encouraged to outline work in progress, industrial case studies, or user experiences as short papers. Accepted short papers will be presented as posters in dedicated sessions, allowing to present advances achieved since submission. Submitted papers should be anonymous, are required to describe original unpublished work and must not be under consideration for publication elsewhere.
PUBLICATIONS:
After the conference, papers and presentations will be published on the ECSI website together with the keynote presentations (subject to confidentiality issues) and tutorial documents. In addition, the accepted and presented papers will be published in IEEE Xplore. The authors of the best regular papers may be invited to prepare an extended manuscript for journal publication.
EMBEDDED TUTORIALS:
Proposals for half-day (4 hours) embedded tutorials on specific topics around any of the four workshops will be accepted depending on topic relevance and evidence of a comprehensive agenda. A one page description of the tutorial including title, presenters, contents, and the relevant track(s) should be sent to fdl2012@ecsi.org. A maximum of three tutorial authors is recommended. Accepted tutorials will get one free registration to the Forum per tutorial.
PANELS, SPECIAL SESSIONS, WORKING GROUPS, PROJECT MEETINGS, DEMONSTRATIONS:
Proposal for special sessions (panels, working sessions, standardization or user group meetings, etc.) around any of the four TA tracks are invited and will be accepted depending on their relevance and interest to the audience. They will be embedded in regular workshops. A one page description including title, participants, contents, and the relevant track(s) should be sent to fdl2012@ecsi.org. Companies, universities or other organizations wishing to demonstrate innovative tools and environments for the topics described above should send proposals to fdl2012@ecsi.org.
Important Dates
Paper submission deadline: 02 April 2012
Special session & embedded tutorial proposal deadline: 09 April 2012
Notification of acceptance: 30 May 2012
Final versions of accepted papers & presenters' registration: 30 July 2012
Proposals for on-site meetings: 30 August 2012
FDL 2012: 18-20 Sept 2012
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Beijing, China June 16, 2012
Co-located with PLDI 2012,
http://safari.ece.cmu.edu/MSPC2012/
Abstract deadline: March 5, 2012 (11:59pm EST)
Paper deadline: March 12, 2012 (11:59pm EDT)
Notification: April 23, 2012
Final submission: May 1, 2012
Memory continues to be a major bottleneck in almost all computing systems. It is becoming more so as more cores and agents are sharing parts of the memory system and as applications that run on the cores are becoming increasingly data intensive. Continuing the tradition of six previous successful incarnations, MSPC 2012 will provide a forum for publishing and discussing all aspects of memory performance and correctness on a variety of systems (multi-core, desktop, embedded, server/cloud, high-performance computing, sensor, etc) and related software and hardware innovations at various levels of the technology stack. We invite new submissions that tackle issues in memory system performance, efficiency, correctness, and dependability in both hardware and software layers. Example areas of interest include but are not limited to the following:
- Hardware, software, and hybrid techniques for better memory performance, correctness, reliability, efficiency
- Memory hierarchy design for chip multiprocessors (CMPs)
- Emerging memory technologies (e.g., Phase Change Memory, MRAM)
- Characterization and analysis of memory systems performance
- Insightful experimental evaluation and analysis of memory-intensive workloads
- Static and dynamic techniques for understanding and improving memory performance and efficiency
- Managed memory and garbage collection optimizations
- Hardware and software techniques for ensuring memory safety and detecting memory-related bugs
- Hardware and software memory models and their impact on programmability and performance
- Memory system issues in accelerator-based computing (e.g., GPGPU)
- Memory system issues in embedded computers and tiny devices
- Prefetching, compression, latency tolerance techniques for memory
- Memory power and energy management techniques
- Memory reliability management techniques
Software, hardware, and hybrid approaches are encouraged. In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.
Submission Guidelines: We encourage the submission of not-fully-polished but provocative short papers (6--8 pages; 8 pages maximum) or position abstracts
(1--2 pages; 2 pages maximum). Paper submissions should use standard ACM SIGPLAN conference format (10pt). Copies of accepted papers will be made available at the workshop and published in the ACM digital library. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work.
Electronic System Level Synthesis Conference
San Francisco, California, USA June 2-3, 2012 www.ecsi.org/eslsyn
Workshop Description
The ever-increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementations are needed for designing both HW and SW parts. ESL design does not only provide system architects with the right tools to make the right decisions about the system architecture, it includes the methodologies and techniques that correlate the ESL model. A well-connected ESL-to-implementation design flow is needed.
The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cycle time all together, breaking the trend to compromise on the evaluation of various design implementation options. Designing at higher levels of abstraction is a viable way to better cope with the system design complexity, to verify earlier in the design process and to increase code reuse.
The Electronic System Level Synthesis Conference ESLsyn focuses on automated system design methods that enable efficient modelling of systems to provide the capability to synthesize HW platforms and embedded software with particular aspects related to synthesis.
Topics
ESLsyn will focus on the five key tasks related to the design and verification of complex, programmable electronic products:
- The development of product architectures and specifications, including the incorporation and configuration of IP
- The mapping of applications to a product specification, including hardware/software partitioning and processor optimization
- The creation of pre-silicon, virtual hardware platforms for software development
- The determination/automation of a hardware implementation for that architecture
- The development of reference models for verifying the hardware
Furthermore, ESLsyn addresses:
- Cyber-Physical System/System/Platform related to ESL design flow
- High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis for HW Design in cooperation with the ESL design flow
- Embedded Software Synthesis that is used into the ESL design flow
The above list is not an exhaustive list of topics addressed by ESLsyn ; contributions related to ESLsyn problems in general not listed here are highly welcome. Submissions may be theoretical scientific papers, research in progress, case studies, tool use cases and best practice, as well as industry experiences.
Important Information for Authors
Authors must follow the paper submission guidelines. Details can be found at http://www.ecsi.org/eslsyn . Questions, contact office@ecsi.org.
Important Dates
Paper Submission Deadline: March 23, 2012
Notification of Acceptance: May 14, 2012
Full Final Paper Submission: May 14, 2012
Copyright Forms: May 14, 2012
Author Registration: May 26, 2012
Presentations Submission + Presenter Bio May 26, 2012
Conference Participation
The 8th International Symposium on Applied Reconfigurable Computing
19-23 March 2012, Hong Kong
Web: http://arc2012.hk
Hosted by the Chinese University of Hong Kong and City University Hong Kong
Registration is now open for ARC 2012, with discounted early registration rates until 19th February:
http://arc2012.hk/registration.html
We have an exciting line-up of plenary speakers including:
Prof. Michael J. Flynn, Stanford University Prof. Dr.-Ing. Sorin A. Huss, Technische Universitaet Darmstadt, Germany Prof. Cetin Kaya Koc, University of California Santa Barbara Prof. Wayne Luk, Imperial College London Grant Martin, Chief Scientist, Tensilica Inc
The preliminary program is now available at:
http://arc2012.hk/preliminary.html
http://arc2012.hk/program.html
Two leading Reconfigurable Technology companies: Xilinx & Altera will also offer Industrial workshops at ARC:
http://arc2012.hk/tutorial.html
We would like to acknowledge the generous support from our sponors:
http://arc2012.hk/sponsor.html
The ARC2012 Symposium
Reconfigurable Computing technologies offer the promise of substantial gains in performance and power efficiency over traditional architectures via customising, even at runtime, the topology of the underlying architecture to match the specific needs of a given application.
Contemporary configurable architectures allow for the definition of specific functional and storage units, adapted to the functions, bit-widths and control structures of a given computation. This flexibility enabled by reconfiguration can also be seen as a basic technique for overcoming permanent and transient failures on emerging device structures.
ARC aims at bringing together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this promising technology. This year's symposium will also host a series of international invited speakers to share their insights into the future of reconfigurable technology.
The ARC 2012 proceedings will appear in the Springer Lecture Notes in Computer Science (LNCS) series and also be available in the SpringerLink on-line service. Additionally, the top papers will be invited to submit to a special section of a forthcoming journal issue of Elsevier Microprocessors and Microsystems (MICPRO).
Brian Bailey – keeping you covered
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