Engineering Pop Culture!
Interesting Idea: Floorplan- Cavities can help you
Brian Bailey
2/14/2012 11:04 AM EST
Editor’s Note: several weeks ago I put out a call for design papers for the EDA Designline. As well as receiving some of the traditional design articles, I also got a few from students or other people who were working on an idea but not necessarily a tool that would be available to the community. I thought that it might be nice to present those to you as this will provide some exposure to new ideas that people are working on and perhaps enable the creators to get in touch with people who may be interested in their work. So, if you are interested in having your ideas or research featured here, please send it to me for inclusion in this “Interesting Idea” series.
Introduction
How well you generate or plan your floorplan determines how effectively the SoC Physical Design cycle can be implemented. For bigger designs, hierarchical approach is followed. Traditionally, the shape of the constituent blocks is kept rectilinear due to ease of implementation at both the block level and top level. These blocks limit the scope of placement, clock tree at the SoC Top level. This shortcoming is eased to an extent if we start implementing different floorplan shapes like Ladder shape, Rectilinear shape with cavity, Donut shaped etc.
What is needed for hierarchical design?
There are various reasons because of which a design team takes decision to move to hierarchical based closure:
The example contains only two hierarchical blocks “BLOCK1” and “BLOCK2” apart from the normal hard IPs like ADC, PWM, Memories etc.
It is also assumed that the placement of PLL is limited to the left bottom corner due to design requirements.
Limitation of the above approach
A comparison between flat and hierarchical approach is perfectly depicted in [1]. But here the scope is different. Many a times, we are left we no other option but to follow a hierarchical based flow.
One of the problems that an engineer would come across is clock tree synthesis. As shown in Figure 1, there is no straight line path between the SOG and the PLL. Hence, the clock tree engine would do the routing as shown in Figure2.
(There are other possible clock tree paths as well. For eg, the clock route can sandwich through Block 1 and Block 2. But for simplicity, it has been assumed that such a configuration is not allowed)
As evident by the clock path, it gets detoured due to hard blocks, IPs in the path.
Owing to this, the clock latency increases, this results in tougher proposition to meet timing etc. Also, due to thin channel available for clock route and the routes emanating from pads, routing congestion might arise.
Proposed floorplan: Cavities can help!
Although Figure 3 is self-explanatory in regards to the gain cavities can give us.
There is an appreciable difference in the way clock can be routed. It not only saves us precious routing resources but also facilitates in meeting timing much more comfortably. Similarly if we explore more geometrical shapes, like triangle, circular (or donut), there are high chances that the QoR of the design might improve considerably.
For simplicity, only 2 cavities on one of the blocks is shown here. For more complex designs and more hierarchical partitions, such cavities might increase. One needs to bear in mind that apart from deciding the cavity, we need to give some routing space as well for the clock (or other signal routes as well.
Another extension of this idea could be in case of critical timing paths. Lets assume there is a timing path from PWM2 to SOG which is very critical. The reason this path is becoming critical is because of BLOCK1 present in between. But if such cavity was present, the path could directly pass from PWM2 to SOG and it would be easier to meet timing.
Summary
Instead of just relying on traditional floorplan approach to close hierarchical designs, we should try to explore shapes like triangular, circular or cavity based floorplan. There are definite advantages of this approach. The implementation would depend on design complexities. Also, one needs to balance the number and position of the cavities for optimum results. This should be the way forward and hopefully some EDA vendor would soon come up with a flow to allow such shapes.
References
1. Comparing Flat and Hierarchical approach http://www.eetasia.com/ART_8800617695_480100_TA_fca24777.HTM
Author's Bio
Sunit Bansal is Tech Lead at Smartplay Technologies (India), focusing on static-timing analysis and timing closure of complete SOCs. Previously, he was employed with Freescale Semiconductors and holds multiple articles in leading VLSI journals. He holds a bachelor’s degree in electronics and communication from Delhi College of Engineering (Delhi, India).
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Sunit Bansal - Smartplay Technologies, India
Introduction
How well you generate or plan your floorplan determines how effectively the SoC Physical Design cycle can be implemented. For bigger designs, hierarchical approach is followed. Traditionally, the shape of the constituent blocks is kept rectilinear due to ease of implementation at both the block level and top level. These blocks limit the scope of placement, clock tree at the SoC Top level. This shortcoming is eased to an extent if we start implementing different floorplan shapes like Ladder shape, Rectilinear shape with cavity, Donut shaped etc.
What is needed for hierarchical design?
There are various reasons because of which a design team takes decision to move to hierarchical based closure:
- Memory requirement: A huge design would involve lots of computation and memory space. So the design is divided in to number of blocks with each block closure using memory optimally.
- Run times: Run times can be reduced if different blocks are closed in parallel.
- Multi-site project : If different blocks are closed across different global locations, then hierarchical flow is the way to go.
- Schedule Requirement: If there are certain blocks which are not matured and would be delivered a month before Tape-out, then it is advisable to close the design hierarchically and plug the block later on
- Already Frozen / Third Party IPs: If a design contains already frozen IP or a third party IP, then hierarchical flow might be required.
- Design Requirement: Sometimes, there are certain strategic design requirements which make you follow the hierarchical approach.
The example contains only two hierarchical blocks “BLOCK1” and “BLOCK2” apart from the normal hard IPs like ADC, PWM, Memories etc.
It is also assumed that the placement of PLL is limited to the left bottom corner due to design requirements.
Figure 1
Limitation of the above approach
A comparison between flat and hierarchical approach is perfectly depicted in [1]. But here the scope is different. Many a times, we are left we no other option but to follow a hierarchical based flow.
One of the problems that an engineer would come across is clock tree synthesis. As shown in Figure 1, there is no straight line path between the SOG and the PLL. Hence, the clock tree engine would do the routing as shown in Figure2.
(There are other possible clock tree paths as well. For eg, the clock route can sandwich through Block 1 and Block 2. But for simplicity, it has been assumed that such a configuration is not allowed)
As evident by the clock path, it gets detoured due to hard blocks, IPs in the path.
Owing to this, the clock latency increases, this results in tougher proposition to meet timing etc. Also, due to thin channel available for clock route and the routes emanating from pads, routing congestion might arise.
Figure 2
Proposed floorplan: Cavities can help!
Although Figure 3 is self-explanatory in regards to the gain cavities can give us.
There is an appreciable difference in the way clock can be routed. It not only saves us precious routing resources but also facilitates in meeting timing much more comfortably. Similarly if we explore more geometrical shapes, like triangle, circular (or donut), there are high chances that the QoR of the design might improve considerably.
For simplicity, only 2 cavities on one of the blocks is shown here. For more complex designs and more hierarchical partitions, such cavities might increase. One needs to bear in mind that apart from deciding the cavity, we need to give some routing space as well for the clock (or other signal routes as well.
Another extension of this idea could be in case of critical timing paths. Lets assume there is a timing path from PWM2 to SOG which is very critical. The reason this path is becoming critical is because of BLOCK1 present in between. But if such cavity was present, the path could directly pass from PWM2 to SOG and it would be easier to meet timing.
Figure 3
Summary
Instead of just relying on traditional floorplan approach to close hierarchical designs, we should try to explore shapes like triangular, circular or cavity based floorplan. There are definite advantages of this approach. The implementation would depend on design complexities. Also, one needs to balance the number and position of the cavities for optimum results. This should be the way forward and hopefully some EDA vendor would soon come up with a flow to allow such shapes.
References
1. Comparing Flat and Hierarchical approach http://www.eetasia.com/ART_8800617695_480100_TA_fca24777.HTM
Author's Bio
Sunit Bansal is Tech Lead at Smartplay Technologies (India), focusing on static-timing analysis and timing closure of complete SOCs. Previously, he was employed with Freescale Semiconductors and holds multiple articles in leading VLSI journals. He holds a bachelor’s degree in electronics and communication from Delhi College of Engineering (Delhi, India).
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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Rich Krajewski
2/17/2012 1:48 PM EST
I would have included a little more explanation.
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