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EDA/IP Weekly Roundup – Feb 22nd
Brian Bailey
2/22/2012 10:53 AM EST
This is a roundup of news or activities in the past few days that may be of interest to people.
Agilent has introduced a compliance test application for systems using low-power double-data-rate 3 memory. LPDDR3 is a type of dynamic random-access memory technology optimized for embedded and mobile applications. It is ideal for mobile devices like smartphones, due to its low power requirements. LPDDR3 DRAM, with data rates up to 1600 MT/s, is 50 percent faster than current LPDDR2 DRAM. The tool offers flexibility to engineers working with nonstandard operating speeds and voltages, giving them a way to characterize their LPDDR3 designs. The Agilent U7231B LPDDR3 test application, which runs on Agilent Infiniium 9000, 90000A and 90000 X-Series oscilloscopes, provides LPDDR3 physical-layer compliance measurements. Signal access is provided by Agilent’s LPDDR3 BGA probes.
Premier Farnell has announced availability of a comprehensive range of hardware and software ARM design solutions across the Americas through its Newark element14 brand. Developers now have access to information on the ARM® architecture, ARM development tools, source code examples, RTOS, and ARM processor-based devices as well as reference designs from many of the world’s leading semiconductor suppliers. The element14 community connects thousands of practicing engineers across the globe. The Knode on element14 is an intelligent online search and knowledge tool that helps engineers research, select and buy the right solutions for their designs.
Real Intent has announced it is now shipping version 1.5 of its Ascent™ Lint software. Version 1.5 of Ascent Lint adds over 40 new rules for Verilog, VHDL and SystemVerilog designs, covering both RTL and gate-level netlists. These checks help catch bugs and improve design quality early in the design cycle. Ascent Lint improves usability with enhancements to the lint debugger GUI and lint policy configuration utility, a more robust waiving capability, and better lint documentation.
Verific Design Automation has been selected by Blue Pearl Software to support its Blue Pearl Software Suite. The Blue Pearl Software Suite is register transfer level (RTL) analysis software used by field programmable gate array (FPGA) and application specific integrated circuit (ASIC) designers. Verific’s SystemVerilog and VHDL parsers and RTL elaborator have been integrated with Blue Pearl’s leading-edge software used for comprehensive RTL analysis, clock-domain crossing checks (CDCs) and automatic Synopsys Design Constraints (SDC) constraint generation. This announcement corresponds to Blue Pearl Software’s introduction today of version 6.0 of its software suite.
Elliptic Technologies has released the DVB CSA3 Descrambler, a security core that supports the latest generation of conditional access specifications licensed by the European Telecommunications Standards Institute (ETSI) and adopted by the Digital Video Broadcasting (DVB) consortium. In today’s world, consumers expect to experience high quality content and to have the freedom to select and control linear-TV content at home. To meet these demands, the Pay-TV operators need to ensure that the networked home multimedia platforms are more flexible, but at the same time they need to improve the security characteristics of these systems in order to protect their investment in content and services. Elliptic’s DVB-CSAv3 Descrambler can be used in Set-Top Box video decoder SoCs and is offered as a descramble-only core which is capable to descramble payloads at the rate of 4.9 bits/cycle. At 250 MHz for example, the core can descramble 1.2 Gbps of traffic.
Cyclos Semiconductor has announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, that AMD has successfully implemented Cyclos’ low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only APU performance but also with the lowest possible power consumption.
Cadence Design Systems has announced availability of new IP cores, including 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable deployment of SoCs for networking and high-performance computing. Cadence has more than 50 tape-outs of Ethernet designs spanning from 1 GbE up to 40 GbE. Their Ethernet solutions include capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Agilent has introduced a compliance test application for systems using low-power double-data-rate 3 memory. LPDDR3 is a type of dynamic random-access memory technology optimized for embedded and mobile applications. It is ideal for mobile devices like smartphones, due to its low power requirements. LPDDR3 DRAM, with data rates up to 1600 MT/s, is 50 percent faster than current LPDDR2 DRAM. The tool offers flexibility to engineers working with nonstandard operating speeds and voltages, giving them a way to characterize their LPDDR3 designs. The Agilent U7231B LPDDR3 test application, which runs on Agilent Infiniium 9000, 90000A and 90000 X-Series oscilloscopes, provides LPDDR3 physical-layer compliance measurements. Signal access is provided by Agilent’s LPDDR3 BGA probes.
Premier Farnell has announced availability of a comprehensive range of hardware and software ARM design solutions across the Americas through its Newark element14 brand. Developers now have access to information on the ARM® architecture, ARM development tools, source code examples, RTOS, and ARM processor-based devices as well as reference designs from many of the world’s leading semiconductor suppliers. The element14 community connects thousands of practicing engineers across the globe. The Knode on element14 is an intelligent online search and knowledge tool that helps engineers research, select and buy the right solutions for their designs.
Real Intent has announced it is now shipping version 1.5 of its Ascent™ Lint software. Version 1.5 of Ascent Lint adds over 40 new rules for Verilog, VHDL and SystemVerilog designs, covering both RTL and gate-level netlists. These checks help catch bugs and improve design quality early in the design cycle. Ascent Lint improves usability with enhancements to the lint debugger GUI and lint policy configuration utility, a more robust waiving capability, and better lint documentation.
Verific Design Automation has been selected by Blue Pearl Software to support its Blue Pearl Software Suite. The Blue Pearl Software Suite is register transfer level (RTL) analysis software used by field programmable gate array (FPGA) and application specific integrated circuit (ASIC) designers. Verific’s SystemVerilog and VHDL parsers and RTL elaborator have been integrated with Blue Pearl’s leading-edge software used for comprehensive RTL analysis, clock-domain crossing checks (CDCs) and automatic Synopsys Design Constraints (SDC) constraint generation. This announcement corresponds to Blue Pearl Software’s introduction today of version 6.0 of its software suite.
Elliptic Technologies has released the DVB CSA3 Descrambler, a security core that supports the latest generation of conditional access specifications licensed by the European Telecommunications Standards Institute (ETSI) and adopted by the Digital Video Broadcasting (DVB) consortium. In today’s world, consumers expect to experience high quality content and to have the freedom to select and control linear-TV content at home. To meet these demands, the Pay-TV operators need to ensure that the networked home multimedia platforms are more flexible, but at the same time they need to improve the security characteristics of these systems in order to protect their investment in content and services. Elliptic’s DVB-CSAv3 Descrambler can be used in Set-Top Box video decoder SoCs and is offered as a descramble-only core which is capable to descramble payloads at the rate of 4.9 bits/cycle. At 250 MHz for example, the core can descramble 1.2 Gbps of traffic.
Cyclos Semiconductor has announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, that AMD has successfully implemented Cyclos’ low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only APU performance but also with the lowest possible power consumption.
Cadence Design Systems has announced availability of new IP cores, including 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable deployment of SoCs for networking and high-performance computing. Cadence has more than 50 tape-outs of Ethernet designs spanning from 1 GbE up to 40 GbE. Their Ethernet solutions include capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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