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Cadence book preview: Advanced Verification Topics
Brian Bailey
2/28/2012 1:57 PM EST
Bishnupriya Bhattacharya, John Decker, Gary Hall, Nick Heaton, Neyaz Khan, Zeev Kirshenbaum, Efrat Shneydor
From the Preface:
The statement “it's a digital world” is a gross simplification of reality. There is no doubt that digital content in electronics design is growing geometrically with Moore's law. However, the addition of integrated analog functions, third-party IP, power management, and software is creating an exponentially-scaled verification problem. Furthermore, this scaling virtually guarantees that inconsistent verification approaches will introduce problems because every project involves multiple, often third-party, global project teams. The convergence of new functionality, exponentially-scaled verification, and distributed teams at advanced nodes such as 20 nm creates operational pressure as companies try to profitably meet the verification requirements of modern Systems on Chip (SoCs). Following the conventional engineering approach to address a huge system, industry-leading teams established a controlled, working base for their verification environment and then built upon that base. Those teams built and selected the Universal Verification Methodology (UVM) standard from Accellera as that base because it is architected to scale with the growing size of digital verification. As the UVM base expands, verification managers and team leaders are now asking “what's next?”
The answer to that question depends on the requirements that SoC verification adds on top of digital verification. An SoC that a team assembles from internal and 3rd-party hardware IP may be primarily digital, but it clearly needs to integrate verification IP (VIP) from multiple sources. If the commercial differentiation of the SoC depends on unique features, then mixed signal and low power are likely to be critical next steps. Verification capacity and the means to automate a comprehensive verification plan are the areas of focus when the SoC is so large and complex that it can only be implemented in the latest available node.
Of these requirements, VIP integration is the most common. Today, the UVM language standard is IEEE 1800 SystemVerilog, but many UVM users need to access VIP written in IEEE 1647 e or IEEE 1666 SystemC. Because many SystemVerilog verification teams would like to easily integrate VIP or models written in different languages, it is essential that the UVM is extended to support multi-language, interoperable verification environments. Doing so builds on the reuse inherent in the UVM and preserves the quality coded into the existing VIP…
Chapter listing:
Chapter 1: Introduction to Metric-Driven Verification
Chapter 2: UVM and Metric-Driven Verification for Mixed-Signal
Chapter 3: Low-Power Verification with the UVM
Chapter 4: Multi-Language UVM
Chapter 5: Developing Acceleratable Universal Verification Components (UVCs) Featured Chapter
Chapter 6: Summary
Chapter 5: Developing Acceleratable Universal Verification Components (UVCs) Featured Chapter
The acceleratable Universal Verification Methodology (UVM) packages allow portions of a standard UVM environment to be accelerated using a hardware accelerator. The extended UVM acceleration packages include support for SystemVerilog and the e high-level verification languages (HVLs). Though this chapter only discusses UVM, acceleration for both the Open Verification Methodology (OVM) and UVM are supported. So, any references to UVM equally apply to OVM.
The purpose of extending UVM to include hardware acceleration is to enable the verification environment to execute faster. Hardware acceleration can dramatically increase run time performance and, therefore, allow more testing to be done in a shorter amount of time, and making the verification engineer more productive.
The following sections can be found in part 1
Introduction to UVM Acceleration – In this segment
UVC Architecture – In this segment
Coming in the next editions are:
UVM Acceleration Package Interfaces
SCE-MI Hardware Interface
Building Acceleratable UVCs in SystemVerilog
Building Acceleratable UVCs in e
Collector and Monitor
The book can be purchased from Amazon using this link, and when I looked today it was priced at just $46.85.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
From the Preface:
The statement “it's a digital world” is a gross simplification of reality. There is no doubt that digital content in electronics design is growing geometrically with Moore's law. However, the addition of integrated analog functions, third-party IP, power management, and software is creating an exponentially-scaled verification problem. Furthermore, this scaling virtually guarantees that inconsistent verification approaches will introduce problems because every project involves multiple, often third-party, global project teams. The convergence of new functionality, exponentially-scaled verification, and distributed teams at advanced nodes such as 20 nm creates operational pressure as companies try to profitably meet the verification requirements of modern Systems on Chip (SoCs). Following the conventional engineering approach to address a huge system, industry-leading teams established a controlled, working base for their verification environment and then built upon that base. Those teams built and selected the Universal Verification Methodology (UVM) standard from Accellera as that base because it is architected to scale with the growing size of digital verification. As the UVM base expands, verification managers and team leaders are now asking “what's next?”
The answer to that question depends on the requirements that SoC verification adds on top of digital verification. An SoC that a team assembles from internal and 3rd-party hardware IP may be primarily digital, but it clearly needs to integrate verification IP (VIP) from multiple sources. If the commercial differentiation of the SoC depends on unique features, then mixed signal and low power are likely to be critical next steps. Verification capacity and the means to automate a comprehensive verification plan are the areas of focus when the SoC is so large and complex that it can only be implemented in the latest available node.
Of these requirements, VIP integration is the most common. Today, the UVM language standard is IEEE 1800 SystemVerilog, but many UVM users need to access VIP written in IEEE 1647 e or IEEE 1666 SystemC. Because many SystemVerilog verification teams would like to easily integrate VIP or models written in different languages, it is essential that the UVM is extended to support multi-language, interoperable verification environments. Doing so builds on the reuse inherent in the UVM and preserves the quality coded into the existing VIP…
Chapter listing:Chapter 1: Introduction to Metric-Driven Verification
Chapter 2: UVM and Metric-Driven Verification for Mixed-Signal
Chapter 3: Low-Power Verification with the UVM
Chapter 4: Multi-Language UVM
Chapter 5: Developing Acceleratable Universal Verification Components (UVCs) Featured Chapter
Chapter 6: Summary
Chapter 5: Developing Acceleratable Universal Verification Components (UVCs) Featured Chapter
The acceleratable Universal Verification Methodology (UVM) packages allow portions of a standard UVM environment to be accelerated using a hardware accelerator. The extended UVM acceleration packages include support for SystemVerilog and the e high-level verification languages (HVLs). Though this chapter only discusses UVM, acceleration for both the Open Verification Methodology (OVM) and UVM are supported. So, any references to UVM equally apply to OVM.
The purpose of extending UVM to include hardware acceleration is to enable the verification environment to execute faster. Hardware acceleration can dramatically increase run time performance and, therefore, allow more testing to be done in a shorter amount of time, and making the verification engineer more productive.
The following sections can be found in part 1
Introduction to UVM Acceleration – In this segment
UVC Architecture – In this segment
Coming in the next editions are:
UVM Acceleration Package Interfaces
SCE-MI Hardware Interface
Building Acceleratable UVCs in SystemVerilog
Building Acceleratable UVCs in e
Collector and Monitor
The book can be purchased from Amazon using this link, and when I looked today it was priced at just $46.85.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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