Chips consume energy and over time that draws power from the battery. Power, when consumed, creates heat which has to be removed from the chip. With the launch of the new iPads, reports about how hot it runs quickly began to spread, and there were just as many people telling us that this was OK and there was no risk of fire. Entertainingly, as I was writing this segment, Portland was having a sizable snow storm and the weather forecaster who followed the report on the hot iPad said: we have had many temperature violations here in the Portland area recently. Who knew that a weather forecaster could have a sense of humor?
Consumption drains batteries and consumers want devices that don’t have to be charged every few hours. Ten years ago, power was not a major design issue. Since then mobile devices have eclipsed desktop environments, and the amount of electronics going into cars means that even that is become an area in which power has to be used very carefully. The consumption of power also creates other problems. Digital logic likes to have nice clean edges and to achieve that that requires very high peak currents and very high frequencies. This creates noise that may affect other more sensitive circuitry, such as analog, or power supplies that droop, or electromigration and many other problems. Power has become an issue at every stage in the design of a chip, from the device level physics, to clock gating, to power sensitive synthesis, to the utilization of multiple power domains, variable frequency and voltage, hardware architectures and even the selection of algorithms and software.
Power, in my opinion, has become a game changer, not just for hardware design teams, but for system design in the bigger context. Every member of the team can adversely affect the power consumption of the final product and in that manner, all team members have an equal responsibility – and yes that includes the software engineers. Power is not an afterthought; it is a discipline that has to become engrained in the team. The EDA industry has to completely re-engineer themselves. No longer is performance and area the only attributes that matter and power optimization is a completely different beast. It doesn’t behave in the nice clean ways that the other two do, it is lumpy, requires a semantic knowledge of intent, and requires knowledge rather than just data. This is probably a bigger change than the one everyone loves to talks about – ESL. While ESL is necessary for system level modeling, optimization and verification, it is just an extension in abstraction. Power has the ability to change the way we think, the ways tools work, the ways in which teams are structured. Power corrupts – is perhaps an interesting way to think about it.
At the simplest level, there are two types of power that a designer cares about, static or leakage power and active or dynamic switching power. Active power is defined by Arvind Shanmugavel Director of Applications Engineering Apache Design, Inc. in the following way:Active power
Active power is the power consumed by the switching activity of the CMOS gates in a design. Power consumed by charging and discharging the interconnect capacitance and the short circuit power in CMOS are both part of active power.Static power
Static power is the power consumed during the standby mode of a design. CMOS gates typically have some amount of sub-threshold leakage current, even when gates are not turned on. The drain to source leakage current is the main component of static power consumption.
It used to be that leakage power was a very small part of the overall power consumption, but as implementation has moved to finer technology nodes, some of the equations change a bit. Each technology node used to operate at lower voltages and this inherently led to less power being consumed per gate. To balance this, the total number of gates increased, so power consumption was likely to stay the same or even rise. However, to see an increase in dynamic power assumes that more is going on in the design, and while that is true, it is not rising exponentially.
Let’s start by making some simplifying assumptions. In a typical chip, 10% of the power consumed is leakage power and 90% is dynamic power. You would think that means that we are only concerned with dynamic power, but you would be wrong. A typical chip, say a cell phone, is in standby mode 90% of the time and when that happens, there is very little dynamic activity in the chip. So 90% of the time we are consuming a small amount of power, and that is draining the battery over a long period of time. This has to be minimized as much as dynamic power.
I asked people what consumes the most power. Venki Venkatesh, Director of Engineering, Atrenta Inc. says: The main culprits tend to be processors, clock networks, and memories. Shawn McCloud VP Marketing at Calypto Design Systems agrees saying: In a typical SoC the processor consumes most of the power. Hardware accelerators are typically memory intensive and as a result memories in these can consume 60-70% of the subsystems power. Arvind Shanmugavel has a slightly different take. He says: Today’s SoC designs are very different from the ones seen a few years ago. We are increasingly seeing a range of IP and communication modules such as USB, HDMI, Graphic, DDRs, GPS, WiFi and Bluetooth that are being integrated into the same piece of silicon. Among these modules, the ones that are dominated by radios such as GPS, WiFi and Bluetooth consume the most amount of power. High speed I/O interfaces including DDRs are also a major contributor of power due to the high data bit rates and large off-chip loading. Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group concurs saying: For mobile clients (handsets, tablets, notebooks), by far, the largest power consumer is the integrated display, followed by the processor. The next consumers would be the wireless link (WiFi or cellular) and DRAM. For servers and standalone desktop PCs (without integrated displays), the processor is the largest consumer. Brad Griffin, director, product marketing, Silicon Realization at Cadence agrees with this breakdown adding that it also depends on the device and the usage profile. For example with the screen he says anyone who uses web, email and games rather than just the phone will consume more power in their large, bright high-definition LCD screens.
Clearly, all parts of the design can benefit from having a careful eye look for ways to save power. In the next article we will examine the stages of the design flow where power can be optimized.
Other parts of this power series include:
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Go back to the root of the EDA Designline Power Series.