EDA DesignLine Blog
Tell us What You Think
We want to know what you thought about this Discussion. Let us know by adding a comment.
Opinion: What Comes After Power Intent Formats?
Qi Wang
4/3/2012 10:39 AM EDT
During the past few years, the EDA industry has made some significant advancements in developing tool flows and methodologies to automate advanced low-power design techniques. Starting with the call for an industry-wide collaboration by the Power Forward Initiative in 2006, the industry is now converging on a power intent–based low-power design methodology. The recent EETimes article titled Power Intent Formats: Light at the End of the Tunnel? provides an excellent review showing how the methodology has evolved over the past five years. Even though there is still a lot of work to be done to deploy and improve the well-adopted power intent–based low-power design methodology, the basic problem is considered to be solved. What’s next?
One may notice that most of the work done in the past few years focused on how to automate advanced low-power design techniques (such as power gating, or dynamic or adaptive voltage frequency scaling) so that such advanced techniques can be deployed in mainstream designs. Areas that have not had equal investment include power estimation and optimization. Given the fact that literally all advanced node designs will become low-power designs, it should not be a surprise to see the industry pick up the momentum and put more investment into power estimation and optimization. There are a few noticeable trends happening now that give us some clue on how the industry is going to evolve to for the next few years.
On one side, the industry needs to move to a higher level of design abstraction, where one of the design requirements is low power. It is well-known that power optimization techniques applied at system and software levels will make a decisive impact on the final system power consumption. However, the fundamental difficulty of addressing power at the system level is how to get accurate-enough power estimation to ensure that any optimization decision at that level counts toward the final implementation.
We will see more research and development in software and system-level power modeling and estimation, complex IP modeling, and extreme low-power IP creation. Some early investment in this area has already shown some promising results. Using emulation, dynamic power analysis can be performed by running real system software directly on the hardware platform. This technology provides a solution for a problem that has intrigued designers for decades: what are the best test vectors that can be used for power estimation? Well, the best test vectors come with the application software itself! Such technology can also be extended to support designs with power gating or power shutoff. Given that most of the systems on the market are using software to control power management features, this technology enables software/hardware co-verification of advanced power management features.
While the industry is shifting more focus into system-level designs, it does not mean we have exhausted our ideas to further reduce power consumption in the traditional RTL-to-GDSII flow. Most of the new ideas to address the “old problems” come from the unification of traditionally separated optimizations into one process. The most significant source of dynamic power consumption in most designs comes from clock tree. As design complexity grows exponentially, clock tree design is becoming rocket science. One approach to address dynamic power consumption is to combine clock tree synthesis and physical optimization such that a single optimization engine can be used to optimize the whole chip together. A new technology called clock concurrent optimization falls into this category. Leakage optimization techniques are mostly tied to advancements in process technology. In contrast to the traditional multi-Vt libraries, new technology targets additional leakage power reduction by enabling the co-optimization of physical design and IC manufacturing processes.
Much effort has been devoted to reduce power consumption in digital circuit design. However, in reality, every modern chip design is actually a mixed-signal one and the industry has not put the same amount of effort into reducing power consumption for analog and mixed-signal designs. However, the situation is changing rapidly. One of the main reasons for the emerging digitally-assisted analog (DAA) design methodology is actually low power, because digital circuitry tends to consume much less power than analog circuitry. Meeting these design challenges requires that EDA tools deliver tighter integration between the analog and digital design environments. Tighter integration enables the sharing of data and constraints, which then enables co-optimization and co-design to achieve the lowest power consumption. One way to provide this integration is to use a common, standard database, such as OpenAccess, across the analog and digital design environments.
The industry will continue to search for new manufacturing processes and techniques to keep the power consumption of chips under control. As a result, new challenges to EDA tools will arise. Some of these new technologies can be fitted into existing design flows and methodologies relatively easily, such as deeply depleted channel and fully-depleted SOI technologies. Some of these new technologies can be embraced by existing design flows and methodologies with a reasonable amount of enhancements, such as 3D-IC and Wide-I/O. Some of these new technologies demand a more disruptive change to existing design flows and methodologies, such as FinFET or tri-gate process.
With the increasing demands on ICs from almost all applications―mobile, wireless, automotive, and medical instruments―we are looking forward to accelerated technology advancements in low-power design. The EDA industry is becoming more important than ever to lead this new era of innovation by developing tools and methodologies to bring new low-power design techniques into real commercial products.
About the Author:
Dr. Qi Wang is the Group Director for the Solutions Marketing at Cadence with a focus on low power and mixed-signal solutions. In this role he interfaces with product marketing, R&D and technical support teams from various product lines to set the solution wide strategy and promote Cadence’s leadership in the advanced low power and mixed-signal designs.
Wang joined Cadence in 1998. Prior to this position, he held various R&D positions in the area of low power synthesis. He was also the leading architect to drive the development of the end-to-end Cadence Low Power Solution. He was the chief architect of Common Power Format, which was contributed to Si2 and became the industry first open power format in early 2007. As the Vice Chair of the Low Power Coalition and the Chair of the Format Working Group at Si2.org, he is also actively driving the industry coalition to promote advanced low power designs and methodologies. He had more than 20 papers published in various international conferences and journals. He also holds 7 US patents and a recipient of Cadence Outstanding Patent Award in 2010. In 2011, he received the Distinguished Service Award from Si2.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
One may notice that most of the work done in the past few years focused on how to automate advanced low-power design techniques (such as power gating, or dynamic or adaptive voltage frequency scaling) so that such advanced techniques can be deployed in mainstream designs. Areas that have not had equal investment include power estimation and optimization. Given the fact that literally all advanced node designs will become low-power designs, it should not be a surprise to see the industry pick up the momentum and put more investment into power estimation and optimization. There are a few noticeable trends happening now that give us some clue on how the industry is going to evolve to for the next few years.
On one side, the industry needs to move to a higher level of design abstraction, where one of the design requirements is low power. It is well-known that power optimization techniques applied at system and software levels will make a decisive impact on the final system power consumption. However, the fundamental difficulty of addressing power at the system level is how to get accurate-enough power estimation to ensure that any optimization decision at that level counts toward the final implementation.
We will see more research and development in software and system-level power modeling and estimation, complex IP modeling, and extreme low-power IP creation. Some early investment in this area has already shown some promising results. Using emulation, dynamic power analysis can be performed by running real system software directly on the hardware platform. This technology provides a solution for a problem that has intrigued designers for decades: what are the best test vectors that can be used for power estimation? Well, the best test vectors come with the application software itself! Such technology can also be extended to support designs with power gating or power shutoff. Given that most of the systems on the market are using software to control power management features, this technology enables software/hardware co-verification of advanced power management features.
While the industry is shifting more focus into system-level designs, it does not mean we have exhausted our ideas to further reduce power consumption in the traditional RTL-to-GDSII flow. Most of the new ideas to address the “old problems” come from the unification of traditionally separated optimizations into one process. The most significant source of dynamic power consumption in most designs comes from clock tree. As design complexity grows exponentially, clock tree design is becoming rocket science. One approach to address dynamic power consumption is to combine clock tree synthesis and physical optimization such that a single optimization engine can be used to optimize the whole chip together. A new technology called clock concurrent optimization falls into this category. Leakage optimization techniques are mostly tied to advancements in process technology. In contrast to the traditional multi-Vt libraries, new technology targets additional leakage power reduction by enabling the co-optimization of physical design and IC manufacturing processes.
Much effort has been devoted to reduce power consumption in digital circuit design. However, in reality, every modern chip design is actually a mixed-signal one and the industry has not put the same amount of effort into reducing power consumption for analog and mixed-signal designs. However, the situation is changing rapidly. One of the main reasons for the emerging digitally-assisted analog (DAA) design methodology is actually low power, because digital circuitry tends to consume much less power than analog circuitry. Meeting these design challenges requires that EDA tools deliver tighter integration between the analog and digital design environments. Tighter integration enables the sharing of data and constraints, which then enables co-optimization and co-design to achieve the lowest power consumption. One way to provide this integration is to use a common, standard database, such as OpenAccess, across the analog and digital design environments.
The industry will continue to search for new manufacturing processes and techniques to keep the power consumption of chips under control. As a result, new challenges to EDA tools will arise. Some of these new technologies can be fitted into existing design flows and methodologies relatively easily, such as deeply depleted channel and fully-depleted SOI technologies. Some of these new technologies can be embraced by existing design flows and methodologies with a reasonable amount of enhancements, such as 3D-IC and Wide-I/O. Some of these new technologies demand a more disruptive change to existing design flows and methodologies, such as FinFET or tri-gate process.
With the increasing demands on ICs from almost all applications―mobile, wireless, automotive, and medical instruments―we are looking forward to accelerated technology advancements in low-power design. The EDA industry is becoming more important than ever to lead this new era of innovation by developing tools and methodologies to bring new low-power design techniques into real commercial products.
About the Author:
Dr. Qi Wang is the Group Director for the Solutions Marketing at Cadence with a focus on low power and mixed-signal solutions. In this role he interfaces with product marketing, R&D and technical support teams from various product lines to set the solution wide strategy and promote Cadence’s leadership in the advanced low power and mixed-signal designs.Wang joined Cadence in 1998. Prior to this position, he held various R&D positions in the area of low power synthesis. He was also the leading architect to drive the development of the end-to-end Cadence Low Power Solution. He was the chief architect of Common Power Format, which was contributed to Si2 and became the industry first open power format in early 2007. As the Vice Chair of the Low Power Coalition and the Chair of the Format Working Group at Si2.org, he is also actively driving the industry coalition to promote advanced low power designs and methodologies. He had more than 20 papers published in various international conferences and journals. He also holds 7 US patents and a recipient of Cadence Outstanding Patent Award in 2010. In 2011, he received the Distinguished Service Award from Si2.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
|
|
|
|
|
Navigate to related information