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John Swan
Aceplorer is a powerful tool that allows you to refine the power exploration at ...
Opinion: Challenges and techniques to meet power budget in complex systems
Brian Bailey
4/5/2012 1:19 PM EDT
Christian Caillon – Founder and manager of C Cube Hightech - Grenoble – France
Reducing the power consumption of electronic equipments is becoming a key differentiator for performances and costs. It is obvious for portable equipments such as smartphones or tablets but also for devices such as set top boxes or TV where thermal problems can occur if power consumption is not well managed. It is really a big challenge for system architects and IC designers to meet the power budget provided by the OEM’s specifications and to make early decisions to manage power. The power reduction methods such as clock gating, power gating, memory gating, DVFS, multi-Vt, transistor dynamic body biasing are now well known but the problem is how to optimize the use of this set of techniques to surely reach the power budget and device specifications. On top of that, engineering time and global effort provided by engineers to meet power specifications is growing with system complexity impacting the time to market. It can be considered that 25% of time is spent by engineers to work on power reduction techniques and analysis. Due to the convergence of multiple applications in smartphones and tablets (telecommunications, internet, games, and multiple connectivity protocols) we can also observe that each new generation of equipment is introducing more complex use cases multiplying the number of power management scenarios.
So it is really a huge task for the architect or SoC designer to compute all those use cases to estimate the battery life and make sure that power targets will be met. To be efficient this power analysis must be performed at a very early stage of the system design to really drive power budget of each subsystem on the board and to manage the low power implementation strategy. Some analysis show that 70% of power saving can be reached at system level, 20% at RTL and only 10% at gate or physical implementation levels.
There are different ways to estimate power at the system level but the most common approach is still to use a set of excel spreadsheets to compute all the power numbers for the different blocks and add them up. This is a statistical approach where the power architect computes in different spreadsheets the activity and power consumption of each block and for each use case. However, by providing only a power number, and not a dynamic profile for the power consumption, the spreadsheet approach makes difficult what-if analysis for power reduction techniques usage. Besides, this technique has very huge limitations when systems are becoming complex and the number of scenarios is growing. Due to the global complexity and number of formulas to manage the maintenance and updates of excel spreadsheets are not easy and too much people dependent.
A second approach is to instrument a virtual platform used for performance analysis and back annotate the SystemC or C model to add power numbers. This approach provides a dynamic power profiles, but has disadvantages of various sorts. First, the performance model does not have natively a notion of voltage domains and some blocks that are meaningful to the power consumption are not relevant to the performance simulation. While we can admit that anything can be programmed in C, adding these notions to the virtual platform will only make the performance model more complex. A second drawback is that it links the availability of power estimation at the system level to the availability of a timed virtual platform. Not only is the virtual platform sometimes available very late in the design cycle, in many companies different virtual platforms coexist depending on their purpose and the timing granularity that is needed. Which virtual platform to instrument then?
The third drawback we see to instrumenting a virtual platform for power is the maintainability of such solution. During the implementation phases of the project, as the different blocks are maturing, and as the power management software will be developed, power simulations for the whole set of use cases will be running on a weekly basis to make sure the project stays on track with regards to power budgets. During that process, power characterization data will be available for all the different blocks at various points in time that will be injected in the system level power simulation to refine the estimation. This would represent an enormous amount of data that needs to be managed by the virtual platform. Again, it will require a significant amount of development to enable this flow of data and model changes in the virtual platform without any risk of breaking the performance modeling capabilities.
An alternative approach is to use a dedicated ESL tool to model and simulate power. This tool would provide early power estimation results based on dynamic or statistical power profiles to drive specifications and allow what if analysis on power architecture (voltage clustering, clock network, voltage regulators) and power management (the use cases). It would also enable a coherent framework to collect all the power related data to refine the power model during the implementation phases, enabling power budget tracking. Aceplorer proposed by Docea Power, introduced on the EDA market few years ago, provides a reliable working environment simplifying the power estimation task for system engineers. Static and dynamic power data coming from RTL or gates simulations, estimations based on gate number and clock frequency, or labs measurements figures will be used to parameterize each block or subsystem of the generic models provided with the Aceplorer library. A hierarchical system description captured on Aceplorer environment and based on power models is used to play with different application use cases and scenarios. Scenarios are composed of test benches controlling power states and durations. To improve accuracy, scenarios must take into account processors loading, bus or I/O traffic data, clock or voltage setting, dynamic switching. When possible system activities can use a VCD format provided by verification engineers or a trace extracted from the activities of a virtual platform allowing then to directly check the effects of power optimization by software.
Analysis reports such as top consumers chart, battery dynamic current analysis, dynamic power distribution allows to understand the system behavior, key power contributors and to make right decisions in time.
The thermal solver proposed with Aceplorer adds value to the simulation by computing the coupling between power and temperature, to get more accurate power profiles and early detection of potential thermal issues.
Very early power analysis at system architecture level (ESL) provides competitive advantages to drive low power hardware and software techniques implementation all along the complete system design flow. Platform power virtualization environment proposed by dedicated ESL tools such as Aceplorer provides a reliable and efficient methodology to meet equipment power budget or significantly increase battery life duration on mobile applications such as smart phones or tablets.
Christian Caillon - Consultant C Cube Hightech
Founder and manager of C Cube Hightech. He has more than 35 years of experience in microelectonics industry,. Prior C Cube Hightech, he worked for STMicroelectronics and STEricsson as design engineering Director and then Tools & Methods Director. He spent more than 15 years in wireless low power applications and chipset developments from GSM to Smart phones applications. He is a graduate of Conservatoire National Des Arts et Metiers in 1980, Paris, France.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
Reducing the power consumption of electronic equipments is becoming a key differentiator for performances and costs. It is obvious for portable equipments such as smartphones or tablets but also for devices such as set top boxes or TV where thermal problems can occur if power consumption is not well managed. It is really a big challenge for system architects and IC designers to meet the power budget provided by the OEM’s specifications and to make early decisions to manage power. The power reduction methods such as clock gating, power gating, memory gating, DVFS, multi-Vt, transistor dynamic body biasing are now well known but the problem is how to optimize the use of this set of techniques to surely reach the power budget and device specifications. On top of that, engineering time and global effort provided by engineers to meet power specifications is growing with system complexity impacting the time to market. It can be considered that 25% of time is spent by engineers to work on power reduction techniques and analysis. Due to the convergence of multiple applications in smartphones and tablets (telecommunications, internet, games, and multiple connectivity protocols) we can also observe that each new generation of equipment is introducing more complex use cases multiplying the number of power management scenarios.
So it is really a huge task for the architect or SoC designer to compute all those use cases to estimate the battery life and make sure that power targets will be met. To be efficient this power analysis must be performed at a very early stage of the system design to really drive power budget of each subsystem on the board and to manage the low power implementation strategy. Some analysis show that 70% of power saving can be reached at system level, 20% at RTL and only 10% at gate or physical implementation levels.
There are different ways to estimate power at the system level but the most common approach is still to use a set of excel spreadsheets to compute all the power numbers for the different blocks and add them up. This is a statistical approach where the power architect computes in different spreadsheets the activity and power consumption of each block and for each use case. However, by providing only a power number, and not a dynamic profile for the power consumption, the spreadsheet approach makes difficult what-if analysis for power reduction techniques usage. Besides, this technique has very huge limitations when systems are becoming complex and the number of scenarios is growing. Due to the global complexity and number of formulas to manage the maintenance and updates of excel spreadsheets are not easy and too much people dependent.
A second approach is to instrument a virtual platform used for performance analysis and back annotate the SystemC or C model to add power numbers. This approach provides a dynamic power profiles, but has disadvantages of various sorts. First, the performance model does not have natively a notion of voltage domains and some blocks that are meaningful to the power consumption are not relevant to the performance simulation. While we can admit that anything can be programmed in C, adding these notions to the virtual platform will only make the performance model more complex. A second drawback is that it links the availability of power estimation at the system level to the availability of a timed virtual platform. Not only is the virtual platform sometimes available very late in the design cycle, in many companies different virtual platforms coexist depending on their purpose and the timing granularity that is needed. Which virtual platform to instrument then?
The third drawback we see to instrumenting a virtual platform for power is the maintainability of such solution. During the implementation phases of the project, as the different blocks are maturing, and as the power management software will be developed, power simulations for the whole set of use cases will be running on a weekly basis to make sure the project stays on track with regards to power budgets. During that process, power characterization data will be available for all the different blocks at various points in time that will be injected in the system level power simulation to refine the estimation. This would represent an enormous amount of data that needs to be managed by the virtual platform. Again, it will require a significant amount of development to enable this flow of data and model changes in the virtual platform without any risk of breaking the performance modeling capabilities.
An alternative approach is to use a dedicated ESL tool to model and simulate power. This tool would provide early power estimation results based on dynamic or statistical power profiles to drive specifications and allow what if analysis on power architecture (voltage clustering, clock network, voltage regulators) and power management (the use cases). It would also enable a coherent framework to collect all the power related data to refine the power model during the implementation phases, enabling power budget tracking. Aceplorer proposed by Docea Power, introduced on the EDA market few years ago, provides a reliable working environment simplifying the power estimation task for system engineers. Static and dynamic power data coming from RTL or gates simulations, estimations based on gate number and clock frequency, or labs measurements figures will be used to parameterize each block or subsystem of the generic models provided with the Aceplorer library. A hierarchical system description captured on Aceplorer environment and based on power models is used to play with different application use cases and scenarios. Scenarios are composed of test benches controlling power states and durations. To improve accuracy, scenarios must take into account processors loading, bus or I/O traffic data, clock or voltage setting, dynamic switching. When possible system activities can use a VCD format provided by verification engineers or a trace extracted from the activities of a virtual platform allowing then to directly check the effects of power optimization by software.
Analysis reports such as top consumers chart, battery dynamic current analysis, dynamic power distribution allows to understand the system behavior, key power contributors and to make right decisions in time.
The thermal solver proposed with Aceplorer adds value to the simulation by computing the coupling between power and temperature, to get more accurate power profiles and early detection of potential thermal issues.
Very early power analysis at system architecture level (ESL) provides competitive advantages to drive low power hardware and software techniques implementation all along the complete system design flow. Platform power virtualization environment proposed by dedicated ESL tools such as Aceplorer provides a reliable and efficient methodology to meet equipment power budget or significantly increase battery life duration on mobile applications such as smart phones or tablets.
Christian Caillon - Consultant C Cube HightechFounder and manager of C Cube Hightech. He has more than 35 years of experience in microelectonics industry,. Prior C Cube Hightech, he worked for STMicroelectronics and STEricsson as design engineering Director and then Tools & Methods Director. He spent more than 15 years in wireless low power applications and chipset developments from GSM to Smart phones applications. He is a graduate of Conservatoire National Des Arts et Metiers in 1980, Paris, France.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
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John Swan
4/15/2012 2:56 AM EDT
Aceplorer is a powerful tool that allows you to refine the power exploration at ESL as you refine the power models. But just as design centers allocate manpower to DFT, for example, they need to allocate engineering manpower to ESL power modeling and scenario simulation with Aceplorer.
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