Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features—although the driving factor for why does differ among them. The primary impetus for low power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement.
For example, the advent of the internet and social media heavily drives the Servers and Networking Market segments where large server clouds and compute farms need to work reliably without overheating; so, their primary concern is reducing the amount of expensive energy required for operation and air conditioning. Other markets such as the multimedia and set top box segments are plugged into the wall but ‘green’ initiatives and the high cost of electricity have forced them into increasing energy efficiency through building in low power techniques similar to those used in the mobile application space.
Power is now a primary requirement for all designs – it’s not just about performance or area anymore and there are several factors that designers need to take into consideration to meet the stringent low power requirements. There are several key components that comprise a low power design and offer methods for controlling power:
- Technology process selection provides a power vs. performance vs. area tradeoff
- Architectural and implementation techniques offers power vs. complexity tradeoffs
- Optimization engines delivers on rapid time-to-market and quality of results
Even process technologies from semiconductor vendors have had to adapt. It used to be that a low-power (LP) process could be used in place of a generic (G) or high-speed/performance (HS/HP) process to provide significant static leakage savings. Back then, the LP process offered typically a 20-30% slower performance than the standard process in exchange for 1.5X less dynamic and up to 50X less static power dissipation which helped extend battery life in most portable designs.
Nowadays at 28nm and below, there are more process variations targeted for low power to meet the various market demands. LP and HS/HP processes continue to be offered where LP is still targeted for mobile applications and extending battery life. However, there are now process variations in between that offer both performance and lower power depending on the application. For example, TSMC offers a 28nm HPL process technology using high-k metal gates that reduces both operation and standby power by about 40% (vs. HP) which is best suited for cellular, wireless and programmable logic devices. They also offer a 28nm HPM process which offers both high performance and low leakage targeted specifically for mobile consumer applications.
The choices of standard cell library architectures for the targeted process have also expanded quite a bit. There used to only be a single standard cell library architecture (fixed cell height) available per process node – one that is characterized for the different voltage threshold (Vt) points. Now, there are several standard cell height (number of grids) choices that offer performance, power and density tradeoffs. For example, Synopsys offers standard cell libraries that are lower in cell height for consumer applications and taller cells for higher performance applications with examples shown below.
In addition to the different cell architectures, channel length variants are also available, exponentially increasing the number of actual cell variants available for libraries. Library vendors, like Synopsys, are creating variations of cells with different channel lengths within each cell. Generally, High-Vt (HVt) libraries are better for power and worse for timing, while Low-Vt (LVt) libraries are much better for timing, but are very leaky. With the availability of libraries containing multiple channel lengths, it is possible to achieve better timing and lower leakage with a Standard-Vt (SVt) cell with a longer channel than an HVt cell with standard channel length. As shown below, for the 28nm HPM process, a shorter length SVt cell would provide 17% lower performance and 30% lower leakage than a standard length LVt cell making it more compelling to use while also saving on an extra mask layer.
Starting at 28nm and below, we are seeing the advent of variations of other low power processes such as fully depleted silicon on insulator (FD-SOI) and fin-based field effect transistors (FinFET). FD-SOI can provide high performance with approximately 35% lower power as compared to traditional MOS-based technologies according to ST Microelectronics. FinFET technologies extends the ability to do 3D transistors which offers up to 50% power savings with about 35% better performance compared to traditional planar transistors at 22nm according to Intel.