As part of the
global survey, Synopsys asked what are some of the top primary
challenges in the design flow with the results shown in the graph
below. Timing closure is always the top design challenge, but power
management has quickly risen to become #2 where this might not have been
included as a primary challenge as recently as 5 years ago.
also asked designers to tell us which power management task presented
the greatest challenge in their design flow. Since multi-voltage design
remains relatively new as an overall power savings technique, it does
pose a set of challenges for deployment in a typical design methodology.
intent-based flows help automate the implementation of power management
techniques. Power intent includes the specification of multiple
voltage power domains, power shutdown modes, isolation, voltage level
shifting and retention behavior. Power intent is captured as a
companion file to the RTL or gate level design using the standardized
IEEE 1801 Unified Power Format (UPF). Early definition of power intent
in the design flow enables downstream tasks in the process to be
automated and driven by a consistent power specification. Used in
conjunction with the RTL or gate netlist of a design, UPF is used
systematically throughout the design process to describe the design’s
Synopsys’ global user survey data shows that most
digital designers are now using a power intent-based methodology and
even more so are planning to deploy it over the next 2 years.
Optimized engines delivers on rapid time-to-market and quality of results
is now a primary requirement for almost all designs and is no longer
limited to mobile applications anymore. The power techniques will
continue to evolve as technology processes continue to shrink and new
design challenges surface.
Consumer demand for new gadgets requires
rapid time to market with limited product lifespan. The EDA tool
selection for developing low power SoCs is based on the ability to
deliver the best quality of results (QoR) with predictable results that
increase design productivity.
Synopsys’ advanced low power
solution provides a comprehensive, silicon-proven approach to low power
design which includes power-awareness built in at every stage of the
design cycle. The advanced low power solution, featuring the GalaxyTM
Implementation Platform, offers all of the low power design techniques
to deliver maximum power savings. Integrated throughout, Synopsys can
increase productivity by providing predictable results early on in the
With over 15 years of proven low power innovations,
Synopsys will continue to invest in providing advanced solutions for the
latest in low power design techniques.
About the Author
Ann White is the product marketing director for GalaxyTM Implementation
Platform products at Synopsys. She has more than 25 years of
experience working in the EDA and semiconductor industries. White has a
BS EECS degree from UC Berkeley.
Synopsys, Inc. Global User Survey, 2011
Other pages you may be interested in: Power 101 series
This posting is part of the EDA Designline
power series and is archived and updated. The root is accessible here
. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.