Power 105: Estimation

Given that power optimization should be a top down processes, it is important to ask the question about accuracy and fidelity of the current estimation tools. To kick this off I will turn to the words of Arvind Shanmugavel Director of Applications Engineering Apache Design, Inc. He says: Power estimation is an accurate science. However, this is only true when we have a fully completed design and the correct set of vectors.

There are two very important parts to his answer. The first is that until the design has been completed, everything is by definition an estimate and is a prediction of what will happen in the design processes. It is more important to be looking for large and relative changes in the power budgets during the early phases of the design processes and not the absolute numbers. We hope that if an estimation tool, let’s say at the transaction level, tells us that one option is better than the other, that it would be true. But it can only base that on how well you may be able to implement both of the options. Maybe you have a very low power way of implementing one of the solutions, you may know better than the tool.

The second important part of the answer is that power, unlike area and performance, is vector related and thus you may have to perform several simulations in order to get a representative sample of the kind of activity in the design. Venki Venkatesh, Director of Engineering, Atrenta Inc. says that in their experience, a 20 percent correlation between RTL to silicon, and a 10 percent correlation between gates to silicon is achievable. Shawn McCloud VP Marketing at Calypto Design Systems agrees saying RTL power estimation is within 10-15% of gate level power estimation. When the problem is constrained more, estimation can become more accurate. For example Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group says: power estimation tools have improved recently, so it is relatively easy to figure out the appropriate level of accuracy for each level of abstraction.

Returning to Arvind, he breaks it down this way: Designers are increasingly moving toward using the early design stages to estimate power. The power estimation process can be abstracted into the following levels:
1.    Electronic System Level (ESL) power estimation - Architecture accurate power estimation

• Activity driven models
• Component classifications
• Micro architecture driven classifications
• Operation modes

2.    Register Transfer Level (RTL) power estimation - State accurate power estimation

• Inference of RTL to gate constructs
• Mapping efficiency of logic
• Wire load model accuracy
• Vector coverage

3.    Gate or netlist level power estimation - Cycle accurate power estimation

• True gate-level power estimation
• Wire load model accuracy
• Vector coverage

4.    Physical power estimation - Cycle accurate and electrically accurate power estimation

• Gate-level power accuracy
• Accurate load
• Accurate timing conditions
• Vector coverage

Other parts of this series include:

• Power 101 – Introduction
• Power 102 – Power in the flow
• Power 103 – Where is power consumed?
• Power 104 – Reducing power consumption
• Power 106 – Verification
• Power 107 – Power delivery network
• Power 108 – Futures

Brought to you by Brian Bailey

---

If you spot an error, would like to propose an improvement or addition to this entry, or anything within this power archive, please let me know by sending me an email. Your comments will be added, and your name will be preserved in the document indicating your participation in its improvement.

Go back to the root of the EDA Designline Power Series.