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Power related papers – DVCon 2012
Brian Bailey
4/23/2012 11:25 AM EDT
DVCon saw a number of papers this year that discussed power issues. They include:
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF
Amit Srivastava, Rudra Mukherjee, Erich Marschner, Chuck Seeley, Mentor Graphics, Sorin Dobre, Qualcomm
Power management is a critical feature of today’s SoCs, almost as important as functionality. IEEE 1801™-2009 UPF enables specification of the intended power management infrastructure for an SoC to enable early verification and to drive implementation. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, the complexity of the power management infrastructure for an SoC similarly requires a hierarchical methodology that enables separation of concerns and supports partitioning, parallel development, and reuse.
In this paper, we propose a hierarchical methodology for the use of IEEE Std 1801™-2009 UPF (aka UPF 2.0) for the specification of power intent for low power SoCs. This methodology enables verification at the IP block level, hierarchical composition of complex system-level power intent specifications from IP block power intent specifications, and automatic consistency checking to ensure that IP block constraints are met by the system in which they are used. The proposed methodology is illustrated in the context of a complex SoC design architecture that was used to validate the concepts.
Download here
The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Himanshu Bhatt, John Decker, Hiral Desai – Cadence
Power-aware design differs from conventional design in both well-understood, as well as, subtle ways. For a typical design today, the RTL describes the functional intent, drives the implementation process and relies on equivalence checking to assure the intent carries through to silicon. In power-aware design, the power format file – either CPF or IEEE 1801 (UPF) – is the specification for the power intent. The functional intent becomes the RTL and the power intent file. While many tools in the end-to-end flow can read the intent, how do we verify that each of these tools has interpreted the intent in the same way? Where does the equivalence checking need to take place for power-aware design?
Download here
Is Power State Table Golden?
Harsha Vardhan, Ankush Bagotra, Neha Bajaj – Synopsys
Independent of the HDL, UPF provides a consistent format to specify power-aware design intent and semantics for verification and implementation. Using the UPF, one can define power supply network, supply network behavior, and additional logical structures such as retention, isolation, and level shifter needed for a low power design. In the UPF, the Power State Table (PST) describes all the possible power states of a design and is used as a golden reference by implementation tools and static verification checkers. With chips becoming complex, hierarchical power domain distribution methodologies are becoming common. As a typical case in complex low power SoCs, hierarchical PSTs need to be merged resulting in several 1000s of states and depending on merging principles, the resultant PST can error prone. This makes verification and implementation a challenging task. It becomes complicated to ensure that all legal states for the design (architectural intent) are captured in the user intended PST before it is considered as ‘golden’. Only extensive and thorough simulation can ensure whether the PST coverage is complete or not before it can be considered golden. If the PST is over constrained, it will result in structural redundancy in implemented design while a under constrained PST will result in structural violations. UPF does not provide the capabilities to describe PST at abstract design level to describe the golden rules for merging, state completion and coverage semantics.
In this paper, we propose a methodology to qualify PST completeness and coherence with respect to High Level Voltage Relationship Constraints (HLVRC). HLVRC defines the relationship between voltage rails at architectural level. Using HLVRC, all possible low power Legal Design States (LDS) can be generated as per low power design rules. These states can become golden for verification and implementation flows. LDS can be used to validate the user specified PST or merged PST for missing or redundant states. In addition, LDS can also be used to check for structural, functional and architectural integrity of an implemented low power design.
Download here
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM
Robert Meyer, Joel Artmann – Medtronic
Given the operational constraints that low power products face, designs must manage every joule of available energy with the utmost care. Furthermore, as chips move to progressively smaller nodes, it is critical to create circuitry whose role is to minimize the effects of leakage current and other such power-stealing phenomena. This circuitry presents a sophisticated verification challenge which needs to be addressed by an equally sophisticated solution.
This paper describes an approach that was used to create a complete low power verification methodology. This methodology verifies the power control logic embedded in the SoC firmware in concert with the SoC‟s power control hardware so that it includes all of the low power control feature in the SoC. This methodology then back-annotates low power verification results into a verification plan to dynamically track progress and quantitatively measure the verification results. All aspects of low power verification are integrated into this methodology including verifying control signal behavior, low power intent of the design and then tying simulation results back into a verification plan to measure verification results. We started with a Common Power Format (CPF) file, which was used to generate a compatible Universal Verification Methodology (UVM) Verification Component (UVC) and PSL assertions devoted to verification of power domain isolation & retention. We then extended these verification components to include other power related features such as clock gating and firmware control. This methodology has cut design and verification cycle times by 50%, while simultaneously significantly increasing the probability of an error-free design. The code created by this approach: the UVCs and assertions, can easily be reused on successive design projects.
Download here
An Integrated Framework for Power Aware Verification
Harsh Chilwal, Manish Jain, Bhaskar Pal – Synopsys
Recent advances in UPF (Unified Power Format) have enabled ways to query the power objects from the UPF (power architecture) data base, and ways to bind checkers without affecting the actual design. In this paper we attempt to leverage these strengths of UPF to ease the specification of power intent (properties/assertions) and instantiation of these in the design for verification. We show that the proposed framework enables the verification engineer to specify its low power intent conveniently in a unified manner and the same intent can be used across different levels of abstractions seamlessly. Though we show the flow using UPF, the methodology is generic and can be implemented/supported in any other power formats.
Download here
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF
Amit Srivastava, Rudra Mukherjee, Erich Marschner, Chuck Seeley, Mentor Graphics, Sorin Dobre, Qualcomm
Power management is a critical feature of today’s SoCs, almost as important as functionality. IEEE 1801™-2009 UPF enables specification of the intended power management infrastructure for an SoC to enable early verification and to drive implementation. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, the complexity of the power management infrastructure for an SoC similarly requires a hierarchical methodology that enables separation of concerns and supports partitioning, parallel development, and reuse.
In this paper, we propose a hierarchical methodology for the use of IEEE Std 1801™-2009 UPF (aka UPF 2.0) for the specification of power intent for low power SoCs. This methodology enables verification at the IP block level, hierarchical composition of complex system-level power intent specifications from IP block power intent specifications, and automatic consistency checking to ensure that IP block constraints are met by the system in which they are used. The proposed methodology is illustrated in the context of a complex SoC design architecture that was used to validate the concepts.
Download here
The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Himanshu Bhatt, John Decker, Hiral Desai – Cadence
Power-aware design differs from conventional design in both well-understood, as well as, subtle ways. For a typical design today, the RTL describes the functional intent, drives the implementation process and relies on equivalence checking to assure the intent carries through to silicon. In power-aware design, the power format file – either CPF or IEEE 1801 (UPF) – is the specification for the power intent. The functional intent becomes the RTL and the power intent file. While many tools in the end-to-end flow can read the intent, how do we verify that each of these tools has interpreted the intent in the same way? Where does the equivalence checking need to take place for power-aware design?
Download here
Is Power State Table Golden?
Harsha Vardhan, Ankush Bagotra, Neha Bajaj – Synopsys
Independent of the HDL, UPF provides a consistent format to specify power-aware design intent and semantics for verification and implementation. Using the UPF, one can define power supply network, supply network behavior, and additional logical structures such as retention, isolation, and level shifter needed for a low power design. In the UPF, the Power State Table (PST) describes all the possible power states of a design and is used as a golden reference by implementation tools and static verification checkers. With chips becoming complex, hierarchical power domain distribution methodologies are becoming common. As a typical case in complex low power SoCs, hierarchical PSTs need to be merged resulting in several 1000s of states and depending on merging principles, the resultant PST can error prone. This makes verification and implementation a challenging task. It becomes complicated to ensure that all legal states for the design (architectural intent) are captured in the user intended PST before it is considered as ‘golden’. Only extensive and thorough simulation can ensure whether the PST coverage is complete or not before it can be considered golden. If the PST is over constrained, it will result in structural redundancy in implemented design while a under constrained PST will result in structural violations. UPF does not provide the capabilities to describe PST at abstract design level to describe the golden rules for merging, state completion and coverage semantics.
In this paper, we propose a methodology to qualify PST completeness and coherence with respect to High Level Voltage Relationship Constraints (HLVRC). HLVRC defines the relationship between voltage rails at architectural level. Using HLVRC, all possible low power Legal Design States (LDS) can be generated as per low power design rules. These states can become golden for verification and implementation flows. LDS can be used to validate the user specified PST or merged PST for missing or redundant states. In addition, LDS can also be used to check for structural, functional and architectural integrity of an implemented low power design.
Download here
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM
Robert Meyer, Joel Artmann – Medtronic
Given the operational constraints that low power products face, designs must manage every joule of available energy with the utmost care. Furthermore, as chips move to progressively smaller nodes, it is critical to create circuitry whose role is to minimize the effects of leakage current and other such power-stealing phenomena. This circuitry presents a sophisticated verification challenge which needs to be addressed by an equally sophisticated solution.
This paper describes an approach that was used to create a complete low power verification methodology. This methodology verifies the power control logic embedded in the SoC firmware in concert with the SoC‟s power control hardware so that it includes all of the low power control feature in the SoC. This methodology then back-annotates low power verification results into a verification plan to dynamically track progress and quantitatively measure the verification results. All aspects of low power verification are integrated into this methodology including verifying control signal behavior, low power intent of the design and then tying simulation results back into a verification plan to measure verification results. We started with a Common Power Format (CPF) file, which was used to generate a compatible Universal Verification Methodology (UVM) Verification Component (UVC) and PSL assertions devoted to verification of power domain isolation & retention. We then extended these verification components to include other power related features such as clock gating and firmware control. This methodology has cut design and verification cycle times by 50%, while simultaneously significantly increasing the probability of an error-free design. The code created by this approach: the UVCs and assertions, can easily be reused on successive design projects.
Download here
An Integrated Framework for Power Aware Verification
Harsh Chilwal, Manish Jain, Bhaskar Pal – Synopsys
Recent advances in UPF (Unified Power Format) have enabled ways to query the power objects from the UPF (power architecture) data base, and ways to bind checkers without affecting the actual design. In this paper we attempt to leverage these strengths of UPF to ease the specification of power intent (properties/assertions) and instantiation of these in the design for verification. We show that the proposed framework enables the verification engineer to specify its low power intent conveniently in a unified manner and the same intent can be used across different levels of abstractions seamlessly. Though we show the flow using UPF, the methodology is generic and can be implemented/supported in any other power formats.
Download here
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
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