Power 108: Powering forward

In my survey, I asked for predictions about where things would be in three years and ten years. They were free to talk about tools, technologies, and modeling. I set the times frames expecting that sort of linear projections would be made for the 3 year period, but when thinking out ten year, you have to think a little outside the box.

In three years:
Venki Venkatesh, Director of Engineering, Atrenta Inc. In the next three years, you can expect formal techniques to improve power reduction, improved physical synthesis, wider support for the power intent formats for accurate verification, and the beginning of true hardware-software co-design. Perhaps the biggest contribution will be a holistic methodology that takes all aspects of chip behavior into account when doing power reduction.

Krishna Balachandran, director, low power verification marketing, Synopsys. From a verification perspective, we can expect to see the following advances:

• Ability to handle giga-scale designs with upwards of 200M gates and hundreds of power domains
• Robust hierarchical flow for verification of LP designs
• Usage and support for simulation-only directives in the power intent specification
• Evolution of advanced debug capability for LP verification
• Widespread use of LP assertions to detect design bugs, leading to EDA vendors providing an extensive, user-controlled infrastructure for the same
• Enhanced LP testbench and coverage technology
• Selective use of formal technology for LP verification

Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group

• Continued use of improved semiconductor processes
• Further extended use of DVFS in more fine-grained power domains and “dark silicon” architectures that turn off large sections of the processor and system.
• Continued increase in application-specific or algorithm-specific processing blocks on processors

Shawn McCloud  VP of Marketing - Calypto
Architectural synthesis tools for power optimization becoming main stream. I’d expect to see high level synthesis to become power aware which will enable a wider optimization scope than what is available at RTL. I’d expect to see power format standards evolve to the support power intent at the ESL level.

Pete Hardee, director, product marketing, Solutions Marketing at Cadence. Lots of good stuff is happening in low-power design. Within the next three years we are likely to see:

• Increased focus on low-power memory interfaces (LP-DDR, DDR4) and power-optimized platform software
• Rich verification components based on UVM-LP to help automate power-aware verification
• Better automation for the more exotic low power design techniques, and some new ones (including new advanced clocking techniques)
• FinFET becomes widespread, giving advantages of new process nodes without leakage getting further out of control
• Usable power estimation at the ESL-TLM level

In ten years
Venki Venkatesh, Director of Engineering, Atrenta Inc. In ten years, hardware software co-design becomes a mainstream reality. Software is no longer written for chips; chips are built to support software. At the circuit level, new transistor circuits will be invented that require substantially less power than today’s designs.

Krishna Balachandran, director, low power verification marketing, Synopsys

• Widespread support for LP testbench and verification methodologies
• Multi-core LP simulation capability
• Analog/Mixed-Signal LP verification capabilities
• Widespread use of formal technologies for LP verification
• Integration between system-level and SoC-level verification
• Evolution of a standard to communicate LP behavior for IP blocks
• Easy-to-use, context-sensitive verification of IP blocks

Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group

• Extending DVFS to components outside the SOC (e.g. memory and storage systems)
• Improved display technologies, such as improved LED and backlight distribution techniques or greater use of more efficient OLED displays
• TSV (Through-Silicon Vias) to improve 3D integration and lower power interfaces
• Revolutionary new battery technologies
• More power efficient wireless technologies

Pete Hardee, director, product marketing, Solutions Marketing at Cadence. Within the next 10 years, we’ll see new categories of devices with different human-machine interfaces, more integrated with their users (e.g. wearable computing) and utilizing all kinds of energy harvesting techniques (motion, solar, temperature etc.)

I am surprised that there is no mention of non-silicon technologies in there. Only one mention of energy harvesting, and only a side mention of different battery technologies such as fuel cells. What do you think? What are they missing?

Other parts of this series include:

• Power 101 – Introduction
• Power 102 – Power in the flow
• Power 103 – Where is power consumed?
• Power 104 – Reducing power consumption
• Power 105 – Estimation
• Power 106 – Verification
• Power 107 – Power delivery network

Brought to you by Brian Bailey

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