Gearing Up for DAC – Above RTL

5/22/2012 5:26 PM EDT

Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.

Click here for a list of verification demos.

Atrenta

SpyGlass Lint and more: Atrenta will demo the full spectrum of capabilities from the SpyGlass linting tool.  They will also explore their new Advanced Lint capability, which includes FSM checks, dead code checks and a unique cyclomatic complexity analysis.

SpyGlass Power: Atrenta will demo their complete power management and optimization flow.  Power estimation, verification, and advanced reduction, including autofix and sequential equivalency checking will all be shown.

Booth #2230

Calypto

Catapult Platform - This session overviews the Calypto ESL design flow -- Catapult for high-level synthesis and SLEC for sequential formal equivalence checking, which together reduce the overall design and verification effort. Catapult is a production proven SystemC/C++ high-level synthesis solution, and when coupled with SLEC provides a complete ESL hardware implementation flow. This session highlights key topics such as language abstraction, control-logic synthesis, ECOs, verification flow and interplay with TLM platforms.

Booth #1226

Duolog

Socrates Bitwise manages HW/SW register, memory-map and interface definitions for IPs, subsystems or SoCs and provides a single-source specification enabling auto-generation of the views required for design, verification, software and integration teams. Existing and new IP are easily handled with an environment that supports architectural planning, IP import, IP creation, and view generation.

Socrates Weaver is a tool for IP integration. The rules-based integration methodology employed by Weaver maximizes the potential for IP, subsystem and system reuse. Rules are high-level specifications of integration intent that are synthesized to create the low-level connections. Because of the high level of abstraction, a single rule can result in hundreds, or even thousands, of individual correct-by-construction connections.

Socrates Spinner - Modern SoC devices typically support multiple static and dynamic operating modes. This can result in thousands of top-level signals that need to be mapped to hundreds of I/O pins according to the target application. Socrates Spinner manages this increasingly complex area by specifying and auto-generating all of the logic associated with the chip I/O layer.

Socrates Sequencer - SoCs and their associated IPs contain metadata used by multiple project stakeholders operating within different domains. Sequencer allows for the formal capture of sequences relating to accesses of memory mapped elements such as registers and bitfields and the constraints between these. The sequence information is stored alongside the IP metadata and can be used to auto generate operational and verification sequence views. The sequencing language extracts the formal description of the hardware/software interface in order  to allow a large array of collateral generation such as: documentation; processor based system verification test cases and constraint checker code; HVL assertions, constraints and sequences; firmware hardware access layer API and implementation.

Booth #1520

Forte Design Systems

Cynthesizer™ High-Level Synthesis is used by design teams who want to reduce time-to-market pressures by designing at a higher level of abstraction and need substantial improvements in circuit size and power. Forte’s synthesis technology and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. At DAC, Forte will demonstrate an ARM-based image processing system with control- and datapath-type blocks highlighting complex hierarchy, custom TLM interfaces and other advanced features.

Product: CellMath Floating Point IP is used by leading graphics providers in more than 100-million mobile devices worldwide. With Forte’s Floating Point IP, designers get a high quality of results for area and performance from RTL or from SystemC.

Booth #1430

Real Intent

Ascent Lint includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. The demonstration of Ascent Lint will feature its fast execution, ease-of-use and reduced rule-set to deliver comprehensive analysis.

Booth #926

Vayavya Labs

provides leading-edge solutions to accelerate embedded software and firmware development. Its patented device-driver generation technology provides a 10x productivity boost by synthesizing driver code from specs, enabling silicon providers and system vendors to ensure timely delivery of the necessary OS ports and board support packages (BSPs). The programmatic spec capture can be leveraged to define a common pre-silicon to post-silicon validation methodology to streamline verification, lowering R&D cost. Vayavya Labs was recently included on the EE Times Silicon 60. They will demonstrate their Accelerated BSP Development methodology, featuring device-driver synthesis, as well as their System-Level Validation solution.

Booth #710