In the recent power series on EDA Designline, you will have noted many people saying that the greatest opportunities for saving power are early in the design process. For many companies today, that means RTL, but one company is pushing much further up the abstract ladder to ESL. Also, thermal management is becoming a big issue for chips and especially significant when 2.5 or 3-D IC are considered.
Docea Power is a company tackling system level power, thermal analysis and modeling and they have just announced version 3.0 of their Aceplorer tool. It now includes an event scheduler for enhanced scenario creation capabilities and support for thermal models generated by AceThermalModeler for coupled power and thermal simulations capabilities. The event scheduler complements the existing timed flow chart creation and vcd import capabilities. In addition, they have announced AceThermalModeler 1.1 with an enhanced 3D viewer for fast model debugging.
Aceplorer models and optimizes electronic design power and thermal consumption for early architecture exploration, architecture validation and power budget tracking during electronic design implementation stages, and AceThermalModeler creates compact RC thermal models for complete systems from SoCs to System-in-Packages (SiP), 3-D ICs to complete boards.
Aceplorer 3.0’s new features include an event scheduler to automate the creation of timed scenarios from parallel tasks and workload definitions with different arbitration schemes, along with the support for thermal models created with AceThermalModeler. The event scheduler complements the existing timed flow chart creation and vcd import capabilities already in place and used to automate the creations of use cases.
More information can be found here
or see them at DAC – Booth # 1702Brian Bailey
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