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Industry view: JEDEC on LPDDR3
Kristin Lewotsky
5/25/2012 2:53 PM EDT
In response to surging bandwidth demand from the mobile device market, the JEDEC Solid State Technology Association just released LPDDR3, a new mobile memory standard that boasts a data rate of 1600 Mbps. We sat down with Hung Vuong, Chairman of JEDEC’s JC-42.6 Subcommittee for Low Power Memories to talk about the new standard, memory challenges, and what comes next.
Kristin Lewotsky, Memory Designline: Can you talk about the chronology?
Hung Vuong, JEDEC: About a year and a half ago, we decided to set the goals for LPDDR3. At that time, LPDDR2 had been out in the industry for about four years, so there hadn’t been anything new to address improved bandwidth or mobile or battery-operated applications. About one and a half years to publish a spec was pretty quick. We deferred a lot of LPDDR4 features forward just to get LPDDR3 out in the market.
K.L.: what was the biggest challenge in developing the LPDDR3 standard?
The biggest challenge was timing closure. Basically what we did [with LPDDR3] was increase the performance of LPDDR2 with minimal change. To be able to meet certain timing criteria, timing closure requirements, we added different features to enable us to make that timing.
K.L.: What should vendors developing LPDDR3-compliant devices and systems know about the standard?
H.V.: Two key features that we added from DDR were write leveling and C/A training. Those two features are designed to help us to improve timing queues and timing closure, and make sure that we have good [communications] between the device and the SoC. We also had a requirement to lower I/O capacitance. As we increase the operating frequency, it’s critical for us adjust gains to meet the bandwidth requirement.
K.L.: What’s next?
JEDEC has started work on LPDDR3E, which is an extension of LPDDR3 intended to increase the bandwidth, because the market was already demanding higher bandwidth, even before we came out with the LPDDR3 specification.
K.L.: The DDR4 standard is slated for release later this year. When will we see an LPDDR4 standard?
H.V.: JEDEC has already started the LPDDR4 work, and that will double our LDDPR3 [data rate] and maybe add new features. We need to see what will be proposed and what will be approved, but the idea is that we will address lower power and higher performance.
K.L.: What keeps you up at night?
H.V.: As an engineer, you always want to work on that next great thing. I think that LPDDR3E is next, but [developing] LPDDR4 to meet market requirements is going to be challenging, and we look forward to that challenge.
Did you find this article of interest? Then visit the Memory Designline, where we update daily with design, technology, product, and news articles tailored to fit your world. Too busy to go every day? Sign up for our newsletter to get the week's best items delivered to your inbox. Just click here and choose the "Manage Newsletters" tab.
Kristin Lewotsky, Memory Designline: Can you talk about the chronology?
Hung Vuong, JEDEC: About a year and a half ago, we decided to set the goals for LPDDR3. At that time, LPDDR2 had been out in the industry for about four years, so there hadn’t been anything new to address improved bandwidth or mobile or battery-operated applications. About one and a half years to publish a spec was pretty quick. We deferred a lot of LPDDR4 features forward just to get LPDDR3 out in the market.
K.L.: what was the biggest challenge in developing the LPDDR3 standard?
The biggest challenge was timing closure. Basically what we did [with LPDDR3] was increase the performance of LPDDR2 with minimal change. To be able to meet certain timing criteria, timing closure requirements, we added different features to enable us to make that timing.
K.L.: What should vendors developing LPDDR3-compliant devices and systems know about the standard?
H.V.: Two key features that we added from DDR were write leveling and C/A training. Those two features are designed to help us to improve timing queues and timing closure, and make sure that we have good [communications] between the device and the SoC. We also had a requirement to lower I/O capacitance. As we increase the operating frequency, it’s critical for us adjust gains to meet the bandwidth requirement.
K.L.: What’s next?
JEDEC has started work on LPDDR3E, which is an extension of LPDDR3 intended to increase the bandwidth, because the market was already demanding higher bandwidth, even before we came out with the LPDDR3 specification.
K.L.: The DDR4 standard is slated for release later this year. When will we see an LPDDR4 standard?
H.V.: JEDEC has already started the LPDDR4 work, and that will double our LDDPR3 [data rate] and maybe add new features. We need to see what will be proposed and what will be approved, but the idea is that we will address lower power and higher performance.
K.L.: What keeps you up at night?
H.V.: As an engineer, you always want to work on that next great thing. I think that LPDDR3E is next, but [developing] LPDDR4 to meet market requirements is going to be challenging, and we look forward to that challenge.
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Did you find this article of interest? Then visit the Memory Designline, where we update daily with design, technology, product, and news articles tailored to fit your world. Too busy to go every day? Sign up for our newsletter to get the week's best items delivered to your inbox. Just click here and choose the "Manage Newsletters" tab.
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