This is a roundup of news or activities in the past few days that may be of interest to people.
Open Core Protocol International Partnership (OCP-IP) has released the OCP 3.1 specification into member review. OCP 3.1 adds several important capabilities, including: Flexible memory barriers, transaction counting parameters, transitions from proprietary OCP RTL.Conf files to the Accellera IP-XACT metadata format, and new cache coherence compliance material.
Silicon Frontline Technology has announced new versions of its products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures, and a new product P2P (Pont-to-Point) for IR drop analysis. F3D has a new segment mode that provides performance improvement as circuit size increases. F3D has improved handling of active and passive devices in addition to support of co-planar structures. These capabilities provide support for newer and more complex geometries. The new version of R3D allows for easy comparison of design enhancements both graphically and with a new layer-by-layer resistance report.
Mentor Graphics has announced the availability of a new DFM Analysis Service based on the Calibre platform for TSMC 40nm and 28nm foundry customers. The service analyzes the customer’s design database in accordance with TSMC’s lithography process checking (LPC) flow. It then delivers a results database with hotspot locations and fixing hints that routers can use to perform corrections. This DFM approach is an attractive alternative for designers taping out relatively few advanced node devices per year.
Mentor also announced that GLOBALFOUNDRIES will use the SmartFill facilities of the Calibre YieldEnhancer product to enable advanced fill techniques for 20nm manufacturing processes. The multi-layer fill analysis and cell-based fill generation capabilities of the SmartFill system help designers deal with complex fill interactions at advanced nodes with minimal impact on circuit performance.
Tanner EDA, has announced the availability of Tanner Analog FastSPICE (T-AFS), offering the Berkeley Design Automation Analog FastSPICE Platform as an add-on to Tanner EDA’s full-flow HiPer Silicon design suite.
Flexras Technologies has announced Wasga Compiler, a software tool for multi-FPGA prototyping. The Compiler is a timing-driven, multi-FPGA partitioning tool for ASIC and SoC prototyping. It can map to any Altera or Xilinx board, both off-the-shelf or custom. Wasga Compiler partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time.
The DDR PHY Interface (DFI) Group has released the DFI 3.1 specification, the latest version of the industry specification that defines an interface protocol between DDR memory controllers and PHYs. The specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. Version 3.1 adds support for the LPDDR3 mobile memory standard for smartphones and tablets, as well as enhancements to the low-power interface and training features. At the same time Cadence has announced support for this new standard in their memory IP offerings.
Open Core Protocol International Partnership (OCP-IP) announces the availability of a new OCP book titled “Introduction to Open Core Protocol: Fastpath to System-On-Chip Design
.” The book provides a hands-on, how-to guide for semiconductor design. Its comprehensive Open Core Protocol introduction includes real “usage examples” not available in the full specification. It is a powerful training aid for university students, those just beginning to use the Open Core Protocol (OCP) socket in real-world design activities, and a valuable reference for experienced users.
Tanner EDA and Australian Semiconductor Technology Corporation are collaborating to deliver analog /mixed signal ASIC design services and solutions globally. ASTC with its manufacturing partners will deliver A/MS IP and Custom ASIC turnkey design services with Tanner EDA tools and flows. ASTC has invested in IP enablement and infrastructure readiness with Tanner EDA tools and flows to deliver low cost A/MS design service solutions to its A/MS ASIC customers globally.
GLOBALFOUNDRIES has selected Synopsys' Yield Explorer® solution as part of their next-phase Yield Management System (YMS) for faster yield ramp based on volume diagnostics. Rapid identification and correction of systematic failure mechanisms is critical to bringing a new technology node to production and driving the yield ramp on new integrated circuit (IC) designs. Yield Explorer Automated Volume Diagnostics allows GLOBALFOUNDRIES to identify the dominant systematic failure mechanisms on early test chips as well as customers' chips, thereby reducing the time to achieve desirable yield levels.
Semiconductor IP provider CAST now offers a debugging solution for 8051 IP cores that requires a single connection instead of the four needed for traditional JTAG debug. The new Single-Wire On-chip Rapid Debugging (SWORD™) interface for the R8051XC2™ microcontroller core connects the 8051 to its debugging unit with just one IC debug port. The popular Joint Test Action Group (JTAG) IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture requires four such connections for the same functionality. SWORD thus requires three less chip pads than JTAG, a significant savings for mobile and other challenging system applications.
Xilinx has made initial shipments of the Virtex®-7 H580T FPGA. Virtex-7 HT devices use Xilinx's stacked silicon interconnect (SSI) technology, featuring up to sixteen 28 Gbps and seventy-two 13.1 Gbps transceivers. These devices are built on TSMC's 28nm high performance/low power process. Monolithic FPGAs are able to integrate only a fourth of the number of 28 Gbps channels. The heterogeneous implementation of Virtex-7 HT devices enables Xilinx to make independent technology choices for the core FPGA and 28 Gbps transceiver die, which avoids burdening the FPGA with high leakage transistors that waste system power. Having 28 Gbps transceivers on silicon separate from the core FPGA fabric further allows for superior noise isolation, enabling best overall signal integrity and system margin.
– keeping you covered
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