Cadence announces results of collaboration on 3D ICs

3D ICs have been in the news a lot recently, and it is sometimes difficult to separate the wheat from the chaff. Cadence hopes that they can make reality a little clearer by telling us today about the progress they have made with TSMC. There are many pieces that have to fall into place before mainstream users can think about adopting this technology, both on the fabrication side and on the design side. Together TSMC and Cadence have taped out a test-chip employing heterogenous chip-on-wafer-on-substrate (CoWoS). TSMC is taking the fabrication, test and assembly process in-house so that they can assure quality and yield as they strive to make this production worthy.

Cadence 3D-IC technology enables multi-chip co-design between digital, custom and package environments incorporating through-silicon vias (TSVs) on both chips and silicon carriers, and supports micro-bump alignment, placement, routing and design for test.  It includes key 3D-IC design IP, such as a Wide IO controller and PHY to support Wide IO memories. Test modules were created using the Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/analog flow, and Allegro system-in-package solutions.

For Cadence, it required extensive rework in many of their tools to enable top die implementation, interposer implementation, analysis and signoff.

I asked John Murphy, group director, Strategic Alliances at Cadence, who they think will be the first users of this type of technology. He believes that memory on processor is a natural fit as it can benefit both from the heterogeneous nature of these chips and the Wide IO that will increase on-chip bandwidth.

TSMC believes that they will be ready for production later this year.

Brian Bailey – keeping you covered

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