Will your next ASIC ever be an FPGA?

Just over a week ago, I moderated a live webinar on EDN titled “When is an FPGA more Appropriate than an ASIC?” The participants were from Xilinx, Altera and Cadence. A repeat event was held at DAC, which I almost moderated, but because of DAC rules I was disqualified because I was also moderating the panel “Can one system model serve everybody?” Richard Goering did a nice write-up of this panel which you can find here.

So Kevin Morris performed the honors. He started by saying that we have heard this story so many times before after each new generation of FPGA is announced.

Brent Przybus director of FPGA product lines for Xilinx was first in line. He said that the time to rethink the way you design is now. An FPGA gets you to market quicker and can provide higher market value and profits. Total cost rather than unit costs must be considered. He said that 3D is a game changer in that programmable devices no longer have to make compromises. With an FPGA the designer can focus on the problem not the technology.

John Costello VP IC design Altera stepped to the plate next. He talked about evolution of FPGAs. In answer to the question, Costello said it has already happened. FPGAs provide the best of both worlds. Wide application scope and speed compared to a general purpose CPU. Use FPGA fabric to connect together ASIC, CPU, DSP, ASAP and others.

Bill Lynch vp eng at Huawei Technologies said he disagrees with everything said before him because the question was wrong. The real question is fixed versus programmable and that does not mean ASIC or FPGA. Most systems are power limited.

Dave Ofelt distinguished engineer at juniper networks concurs that power issues dominate. He said that their ASICs follow an aggressive process geometry track. FPGA gates and RAM have high overhead. FPGAs tend to be slower clock and wider buses. FPGAs are Swiss army knives. Even though total cost may be lower, bean counters will look at lower margins. FPGAs can be good for devices closer to the ports.

Jeanne Trinko Mechler distinguished engineer at IBM provided a chart showing where the space goes in a typical ASIC. 1/2 memory about 1/4 logic. She compared a typical ASIC and FPGA. ASIC logic cells are 50 million compared to 2 million for FPGA. IP is fairly even in the areas of I/O. ASIC chip power 70-80W FPGA 15-20W. ASIC clock 850MHz-1GHz FPGA 200-250MHz.
The final panelist was John Frediani from Advantest who reminded me that I had not got enough sleep the night before.

My take is that the notion of FPGA and ASIC is converging. The most recent FPGA offering contain ASIC components such as processors which run at comparable speeds to those on an ASIC. The FPGAs may even have a slight edge as they are using the latest process technologies whereas most ASICs are still using previous process generations. The same is true of SerDes and other devices. Reprogrammable logic resources will always be larger and slower than ASIC logic, but they use less power and are faster than algorithms running on a processor or DSP. So many ASICs could benefit from having some FPGA-like resources built into them. They can be used for mapping accelerators and parts of an application likely to change over time.

Do you think we will see converged devices in the near future?

Brian Bailey – keeping you covered

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