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EDA/IP Weekly Roundup – June 20th
Brian Bailey
6/20/2012 10:22 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Tanner EDA, TowerJazz and the Science and Technology Facilities Council’s (STFC) Rutherford Appleton Laboratory (UK) has announced development of an advanced sensor for medical imaging applications. This imager was enabled by advanced analog design tools from Tanner EDA and leading-edge CMOS image sensor manufacturing process technology from TowerJazz. The three-sided ‘buttable’ high-resolution high-frame-rate sensor integrates 6.7 million pixels on 50-micron pitch for mammography applications. A unique feature of the device is that it has sensing pixels right up to the edges on three sides of the imager. This allows multiple sensors, manufactured on 200 mm silicon wafers, to be ‘butted’ or ‘tiled’ together in a 2 x 2 arrangement to form a significantly larger imaging area and to meet the requirements for mammography applications. Additionally, any 2 x N sensor arrangements are possible, thus making the device ideal for applications that demand even larger area coverage, such as chest imaging or security scans.
Dolphin Integration announces that the new memory architecture RHEA has now passed the Level 1 criteria of TSMC’s stringent IP9000 qualification program. The Single Port RAM compiler RHEA is suited for consumer applications such as flash controllers and bridge interfaces. Provides higher density with lower power consumption than competing sRAM implementations available at 90 nm LP.
Shocking Technologies has integrated its ESD Simulation Module and design capability for embedded ESD protection into Cadence Design System’s Allegro® PCB technology. Shocking Tech’s ESD Simulation module enables intelligent ESD design, allowing engineers to analyze a system net-by-net for vulnerability to direct ESD pulses and to energy coupling from adjacent nets. Recommendations from the Simulation Module can be incorporated into the layout through automated ESD design rules and embedded design feature integration. System and layout designers will be able to incorporate embedded ESD protection features into system schematics and PCB layouts through the standard Allegro toolbar menu.
Research and Markets has announced its "2012 Interface" report. It provides coverage of the five major application markets including: automotive, computer, consumer, communications, and industrial, as well as regional and product breakdowns. Interface ICs are critical components in the process of connecting electrical signals according to the voltage and current requirements of various transmission lines and hardware buses. These devices are used in systems in a variety of different ways to transfer, route, and time electrical signals among a given system's memory, microprocessor, and various peripherals, and also between interconnected systems. The global interface market saw nearly flat revenue growth from 2010 to 2012 and only a slight gain in total shipment volumes. Databeans expects that sales will actually decline from 2011 to 2012, falling 6 percent to $5.2 billion this year. Meanwhile, shipment volumes will also decline slightly in 2012. These declines were primarily the result of this market's reliance on the computer segment, which did not perform particularly well during 2011. Even so, Databeans expects that this market will see the beginning of a rebound in 2013 and will see growth terms of both sales and shipments over the next five years.
Altera Corporation and Texas Instruments have introduced an RF development kit that eases RF prototyping for systems based on Altera's 28-nm Arria® V FPGAs. The modular Arria V FPGA RF Development Kit includes all the hardware and software needed for RF transmit, receive and digital pre-distortion feedback. The Arria V FPGA RF Development Kit provides RF developers with access to the latest generation of 28-nm FPGAs from Altera, along with the newest analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and clocks from TI. The kit provides 2.5 times more transmit and digital pre-distortion feedback bandwidth than similar solutions and is the industry's first complete main/diversity receive development platform supporting up to 75 MHz of bandwidth.
ON Semiconductor has released a front-to-back process design kit (PDK) for its High-Q™ Integrated Passive Device (IPD) process. The PDK was developed for use with Agilent Technologies’ Advanced Design System (ADS) 2011 EDA software. The High-Q IPD process offers a copper on high resistivity silicon platform, targeted at passive devices such as baluns, filters, couplers, diplexers and matching networks that are used in portable, wireless and RF applications. IPD technology supports fabrication of copper inductors, precision capacitors, and precision resistors.
Cypress Semiconductor and Nuvation Research have announced the production release of a rapid-prototyping solution that simplifies streaming video, images and other data from Altera FPGAs to a host processor at speeds up to 400 Megabytes per second. This solution includes a SuperSpeed USB 3.0 device interface board that connects to Arrow Electronics’ BeMicro SDK (Software Development Kit), the popular FPGA evaluation platform featuring an Altera Cyclone IV FPGA. This new USB 3.0 expansion board enables BeMicro users to prototype a simpler, uncompressed, cost-effective alternative to traditional slower interfaces such as USB 2.0 and Gigabit Ethernet.
Sand 9, a MEMS technology company developing precision timing products for wireless and wired applications, has raised a total of $23 million in its Series C financing round led by Intel Capital with significant participation from Vulcan Capital. Intel Capital and Vulcan Capital join existing investors Commonwealth Capital Ventures, Flybridge Capital Partners, General Catalyst Partners, Khosla Ventures and CSR. Sand 9 will use funds to ramp volume production as they go to market and to expand their product portfolio.
MIPI Alliance and the USB 3.0 Promoter Group have completed the SuperSpeed USB Inter-Chip (SSIC) specification. The specification defines a chip-to-chip USB based internal interconnect for mobile devices as well as other platforms. SSIC offers MIPI Alliance’s M-PHY high bandwidth and low power capabilities combined with SuperSpeed USB performance enhancements. The M-PHYSM interface, a high speed serial interface, targets up to 2.9 Gbps per lane with scalability up to 5.8 Gbps per lane and offers a low pin count and exceptional power efficiency. SuperSpeed USB offers a 5 Gbps signaling rate, up to 10 times faster than Hi-Speed USB (USB 2.0), enhanced protocol and power management and backward compatibility with the existing USB device and software model.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Tanner EDA, TowerJazz and the Science and Technology Facilities Council’s (STFC) Rutherford Appleton Laboratory (UK) has announced development of an advanced sensor for medical imaging applications. This imager was enabled by advanced analog design tools from Tanner EDA and leading-edge CMOS image sensor manufacturing process technology from TowerJazz. The three-sided ‘buttable’ high-resolution high-frame-rate sensor integrates 6.7 million pixels on 50-micron pitch for mammography applications. A unique feature of the device is that it has sensing pixels right up to the edges on three sides of the imager. This allows multiple sensors, manufactured on 200 mm silicon wafers, to be ‘butted’ or ‘tiled’ together in a 2 x 2 arrangement to form a significantly larger imaging area and to meet the requirements for mammography applications. Additionally, any 2 x N sensor arrangements are possible, thus making the device ideal for applications that demand even larger area coverage, such as chest imaging or security scans.
Dolphin Integration announces that the new memory architecture RHEA has now passed the Level 1 criteria of TSMC’s stringent IP9000 qualification program. The Single Port RAM compiler RHEA is suited for consumer applications such as flash controllers and bridge interfaces. Provides higher density with lower power consumption than competing sRAM implementations available at 90 nm LP.
Shocking Technologies has integrated its ESD Simulation Module and design capability for embedded ESD protection into Cadence Design System’s Allegro® PCB technology. Shocking Tech’s ESD Simulation module enables intelligent ESD design, allowing engineers to analyze a system net-by-net for vulnerability to direct ESD pulses and to energy coupling from adjacent nets. Recommendations from the Simulation Module can be incorporated into the layout through automated ESD design rules and embedded design feature integration. System and layout designers will be able to incorporate embedded ESD protection features into system schematics and PCB layouts through the standard Allegro toolbar menu.
Research and Markets has announced its "2012 Interface" report. It provides coverage of the five major application markets including: automotive, computer, consumer, communications, and industrial, as well as regional and product breakdowns. Interface ICs are critical components in the process of connecting electrical signals according to the voltage and current requirements of various transmission lines and hardware buses. These devices are used in systems in a variety of different ways to transfer, route, and time electrical signals among a given system's memory, microprocessor, and various peripherals, and also between interconnected systems. The global interface market saw nearly flat revenue growth from 2010 to 2012 and only a slight gain in total shipment volumes. Databeans expects that sales will actually decline from 2011 to 2012, falling 6 percent to $5.2 billion this year. Meanwhile, shipment volumes will also decline slightly in 2012. These declines were primarily the result of this market's reliance on the computer segment, which did not perform particularly well during 2011. Even so, Databeans expects that this market will see the beginning of a rebound in 2013 and will see growth terms of both sales and shipments over the next five years.
Altera Corporation and Texas Instruments have introduced an RF development kit that eases RF prototyping for systems based on Altera's 28-nm Arria® V FPGAs. The modular Arria V FPGA RF Development Kit includes all the hardware and software needed for RF transmit, receive and digital pre-distortion feedback. The Arria V FPGA RF Development Kit provides RF developers with access to the latest generation of 28-nm FPGAs from Altera, along with the newest analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and clocks from TI. The kit provides 2.5 times more transmit and digital pre-distortion feedback bandwidth than similar solutions and is the industry's first complete main/diversity receive development platform supporting up to 75 MHz of bandwidth.
ON Semiconductor has released a front-to-back process design kit (PDK) for its High-Q™ Integrated Passive Device (IPD) process. The PDK was developed for use with Agilent Technologies’ Advanced Design System (ADS) 2011 EDA software. The High-Q IPD process offers a copper on high resistivity silicon platform, targeted at passive devices such as baluns, filters, couplers, diplexers and matching networks that are used in portable, wireless and RF applications. IPD technology supports fabrication of copper inductors, precision capacitors, and precision resistors.
Cypress Semiconductor and Nuvation Research have announced the production release of a rapid-prototyping solution that simplifies streaming video, images and other data from Altera FPGAs to a host processor at speeds up to 400 Megabytes per second. This solution includes a SuperSpeed USB 3.0 device interface board that connects to Arrow Electronics’ BeMicro SDK (Software Development Kit), the popular FPGA evaluation platform featuring an Altera Cyclone IV FPGA. This new USB 3.0 expansion board enables BeMicro users to prototype a simpler, uncompressed, cost-effective alternative to traditional slower interfaces such as USB 2.0 and Gigabit Ethernet.
Sand 9, a MEMS technology company developing precision timing products for wireless and wired applications, has raised a total of $23 million in its Series C financing round led by Intel Capital with significant participation from Vulcan Capital. Intel Capital and Vulcan Capital join existing investors Commonwealth Capital Ventures, Flybridge Capital Partners, General Catalyst Partners, Khosla Ventures and CSR. Sand 9 will use funds to ramp volume production as they go to market and to expand their product portfolio.
MIPI Alliance and the USB 3.0 Promoter Group have completed the SuperSpeed USB Inter-Chip (SSIC) specification. The specification defines a chip-to-chip USB based internal interconnect for mobile devices as well as other platforms. SSIC offers MIPI Alliance’s M-PHY high bandwidth and low power capabilities combined with SuperSpeed USB performance enhancements. The M-PHYSM interface, a high speed serial interface, targets up to 2.9 Gbps per lane with scalability up to 5.8 Gbps per lane and offers a low pin count and exceptional power efficiency. SuperSpeed USB offers a 5 Gbps signaling rate, up to 10 times faster than Hi-Speed USB (USB 2.0), enhanced protocol and power management and backward compatibility with the existing USB device and software model.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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